DUAL CMOS SyncFIFO™
Integrated Device Technology, Inc.
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
FEATURES:
• The 72801 is equivalent to two 72201 256 x 9 FIFOs
• The 72811 is equivalent to two 72211 512 x 9 FIFOs
• The 72821 is equivalent to two 72221 1024 x 9 FIFOs
• The 72831 is equivalent to two 72231 2048 x 9 FIFOs
• The 72841 is equivalent to two 72241 4096 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 15 ns read/write cycle time FOR THE 72801/72811
• 20 ns read/write cycle time FOR THE 72821/72831/72841
• Separate control lines and data lines for each FIFO
• Separate empty, full, programmable almost-empty and
almost-full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack (TQFP)
• Industrial temperature range (-40
O
C to +85
O
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
72801/72811/72821/72831/72841 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two
72201/72211/72221/72231/72241 FIFOs in a single package
with all associated control, data, and flag lines assigned to
separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B)
contained in the 72801/72811/72821/72831/72841 has a 9-
bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output
data port (QA0 - QA8, QB0 - QB8). Each input port is
controlled by a free-running clock(WCLKA, WCLKB), and two
write enable pins (
WENA1
, WENA2,
WENB1
, WENB2). Data
is written into each of the two arrays on every rising clock edge
of the write clock (WCLKA WCLKB) when the appropriate
write enable pins are asserted.
The output port of each FIFO bank is controlled by its
associated clock pin (RCLKA, RCLKB) and two read enable
pins (
RENA1
,
RENA2
,
RENB1
,
RENB2
). The read clock can
be tied to the write clock for single clock operation or the two
clocks can run asynchronous of one another for dual clock
operation. An output enable pin (
OEA
,
OEB
) is provided on the
read port of each FIFO for three-state output control .
Each of the two FIFOs has two fixed flags, empty (
EFA
,
EFB
)
and full (
FFA
,
FFB
). Two programmable flags, almost-empty
(
PAEA
,
PAEB
) and almost-full (
PAFA
,
PAFB
), are provided for
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
GND
QB
8
QB
7
QB
6
QB
5
QB
4
QB
3
QB
2
QB
1
QA
0
FFA
EFA
OEA
RENA
2
RCLKA
RENA
1
PIN CONFIGURATION
WENA
2
/
LDA
WCLKA
QA
1
QA
2
QA
3
QA
4
QA
5
QA
6
QA
7
QA
8
V
CC
WENA
1
RSA
DA
8
DA
7
DA
6
PAFA
PAEA
WENB
2
/
LDB
WCLKB
WENB
1
RSB
DA
5
DA
4
DA
3
DA
2
DA
1
DA
0
DB
8
DB
7
DB
6
DB
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PN64-1
TQFP,
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FFB
EFB
OEB
RENB
2
RCLKB
RENB
1
GND
V
CC
DB
0
DB
1
DB
2
DB
3
DB
4
QB0
PAEB
PAFB
3034 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
NOVEMBER 1996
DSC-3034/1
5.15
1
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
each FIFO bank to improve memory utilization. If not pro-
grammed, the programmable flags default to empty+7 for
PAEA
and
PAEB
, and full-7 for
PAFA
and
PAFB
.
The 72801/72811/72821/72831/72841 architecture lends
itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion
This FIFO is fabricated using IDTs high-performance sub-
micron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
DA
0
- DA
8
WENA2
WENB2
WCLKB
DB
0
- DB
8
INPUT REGISTER
OFFSET REGISTER
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RESET LOGIC
OUTPUT REGISTER
QA
0
- QA
8
RCLKA
QB
0
- QB
8
RCLKB
3034 drw 01A
5.15
2
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
PIN DESCRIPTIONS
The 72801/72811/72821/72831/72841s two FIFOs, referred
to as FIFO A and FIFO B, are identical in every respect. The
following description defines the input and output signals for
FIFO A. The corresponding signal names for FIFO B are
provided in parentheses.
Symbol
D
A0
-D
A8
D
B0
-D
B8
Name I/O
A Data Inputs
B Data Inputs
Reset
I
I
I
Description
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When
RSA
(
RSB
) is set LOW, the associated internal read and write pointers of array A (B) are
set to the first location;
FFA
(
FFB
) and
PAFA
(
PAFB
) go HIGH, and
PAEA
(
PAEB
) and
EFA
(
EFB
)
go LOW. After power-up, a reset of both FIFOs A and B is required before an initial WRITE.
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the
write enable(s) are asserted.
If FIFO A (B) is configured to have programmable flags,
WENA1
(
WENB1
) is the only write
enable pin that can be used. When
WENA1
(
WENB1
) is LOW, data A (B) is written into the
FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to
have two write enables,
WENA1
(
WENB1
) must be LOW and WENA2 (WENB2) must be HIGH
to write data into the FIFO. Data will not be written into the FIFO if
FFA
(
FFB
) is LOW.
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If
LDA
(
LDB
) is HIGH at reset, this pin operates as a second write enable. If WENA2/
LDA
(WENB2/
LDB
) is LOW at reset this pin operates as a control to load and read the program
mable flag offsets for its respective array. If the FIFO is configured to have two write enables,
WENA1
(
WENB1
) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if
FFA
(
FFB
) is LOW. If the FIFO is configured to
have programmable flags,
LDA
(
LDB
) is held LOW to write or read the programmable flag
offsets.
9-bit data outputs from RAM array A.
9-bit data outputs from RAM array B.
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are asserted.
RSA
,
RSB
WCLKA
WCLKB
Write Clock
Write Enable 1
I
I
WENA1
WENB1
WENA2/
LDA
WENB2/
LDB
Write Enable 2/
Load
I
Q
A0
-Q
A8
Q
B0
-Q
B8
RCLKA
RCLKB
A Data Outputs O
B Data Outputs O
Read Clock
Read Enable 1
I
I
RENA1
RENB1
RENA2
RENB2
OEA
OEB
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
V
CC
GND
When
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are LOW, data is read from FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if
EFA
(
EFB
) is LOW.
When
RENA1
(
RENB1
) and
RENA2
(
RENB2
) are LOW, data is read from the FIFO A (B) on
every LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if
the
EFA
(EFB) is LOW.
Read Enable 2
I
Output Enable
Empty Flag
I
O
When
OEA
(
OEB
) is LOW, outputs D
A0
-D
A8
(D
B0
-D
B8
) are active. If
OEA
(
OEB
) is HIGH, the
outputs D
A0
-D
A8
(D
B0
-D
B8
) will be in a high-impedance state.
When
EFA
(
EFB
) is LOW, FIFO A (B) is empty and further data reads from the output are
inhibited. When
EFA
(
EFB
) is HIGH, FIFO A (B) is not empty.
EFA
(
EFB
) is synchronized to
RCLKA (RCLKB).
When
PAEA
(
PAEB
) is LOW, FIFO A (B) is almost empty based on the offset programmed into
the appropriate offset register. The default offset at reset is Empty+7.
PAEA
(
PAEB
) is synchro
nized to RCLKA (RCLKB).
When
PAFA
(
PAFB
) is LOW, FIFO A (B) is almost full based on the offset programmed into the
appropriate offset register. The default offset at reset is Full-7.
PAFA
(
PAFB
) is synchronized
to WCLKA (WCLKB).
When
FFA
(
FFB
) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
When
FFA
(
FFB
) is HIGH, FIFO A (B) is not full.
FFA
(
FFB
) is synchronized to WCLKA
(WCLKB).
+5V power supply pin.
0V ground pin.
3034 tbl 01
Programmable
Almost-Empty
Flag
O
Programmable O
Almost-Full Flag
Full Flag
O
Power
Ground
5.15
3
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating
Terminal Voltage with
V
TERM
Respect to GND
Operating Temperature
T
A
Temperature Under Bias
T
BIAS
T
STG
I
OUT
Storage Temperature
DC Output Current
Commercial
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
50
Unit
V
°C
°C
°C
mA
3034 tbl 02
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.0
—
Typ.
5.0
0
—
—
Max.
5.5
0
—
0.8
Unit
V
V
V
V
3034 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
3034 tbl 04
NOTE:
1. With output deselected (
OEA
,
OEB
= HIGH).
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
IDT72801
IDT72811
Commercial
t
CLK
= 15, 20, 25, 35ns
Typ.
—
—
—
—
—
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Min.
–1
–10
2.4
—
—
Max.
–1
10
—
0.4
270
Unit
µA
µA
V
V
mA
3034 tbl 05
IDT72821
IDT72831
IDT72841
Commercial
t
CLK
= 20, 25, 35 ns
Typ.
—
—
—
—
—
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC
(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Min.
–1
–10
2.4
—
—
Max.
–1
10
—
0.4
300
Unit
µA
µA
V
V
mA
3034 tbl 06
NOTES:
1. Measurements with 0.4
≤
VIN
≤
VCC.
2. OEA, OEB
≥
VIH, 0.4
≤
VOUT
≤
VCC.
3. Measurements are made with outputs open. Tested at f
CLK
= 20MHz.
Icc limits applicable when using both banks of FIFOs simultaneously.
5.15
4
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
Commercial
IDT72801L12 IDT72801L15 IDT72801L20 IDT72801L25 IDT72801L35
IDT72811L12 IDT72811L15 IDT72811L20 IDT72811L25 IDT72811L35
IDT72821L12 IDT72821L15 IDT72821L20 IDT72821L25 IDT72821L35
IDT72831L12 IDT72831L15 IDT72831L20 IDT72831L25 IDT72831L35
IDT72841L12 IDT72841L15 IDT72841L20 IDT72841L25 IDT72841L35
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable
Almost-Full Flag
Read Clock to Programmable
Almost-Empty Flag
t
SKEW1
Skew Time Between Read
Clock and Write Clock
for Empty Flag and Full Flag
t
SKEW2
Skew Time Between Read Clock
and Write Clock for Programmable
Almost-Empty Flag and
Programmable Almost-Full Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
Min. Max.
—
2
12
5
5
3
0
3
0
12
12
12
—
0
3
3
—
—
—
—
5
83.3
8
—
—
—
—
—
—
—
—
—
—
12
—
7
7
8
8
8
8
—
Min. Max.
—
2
15
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
Min. Max.
—
2
20
8
8
5
1
5
1
20
20
20
—
0
3
3
—
—
—
—
8
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
Min. Max.
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
Min. Max. Unit
—
3
35
14
14
8
2
8
2
35
35
35
—
0
3
3
—
—
—
—
12
28.6 MHz
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
—
28
—
35
—
40
—
42
—
ns
3034 tbl 07
5V
1.1K
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
3034 tbl 08
D.U.T.
680Ω
30pF*
3034 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.15
5
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