NIS5102
High Side
SMART HotPlugt IC/Inrush
Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed for +12 V applications.
This chip includes a time delay for sequencing applications. It has a
dual function OVLO pin that allows multiple units to be ganged
together for simultaneous turn-on and shutdown, allowing units to be
operated in parallel. It allows for user selectable undervoltage and
overvoltage lockout levels. Its unique current limit circuit allows for
adjustable current limit levels with no external power resistor. An
internal temperature limiting circuit greatly increases the reliability of
this device.
Features
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MARKING
DIAGRAM
1
5102QPxH
AWLYWWG
12 PIN PLLP, 9x9 mm
CASE 488AB
x
A
WL
Y
WW
G
•
•
•
•
•
•
•
•
•
•
Integrated Power Device
Power Device Thermally Protected
No External Current Shunt Required
Simultaneous Shutdown and Startup for Parallel Operation
Enable/Timer Pin
Power Good
9.0 to 18 V Input Range
10 mW
Main/Mirror MOSFET Current Ratio 1000:1
Pb-Free Packages are Available
PIN CONNECTIONS
12
11
10
9
8
7
(Bottom View)
13
1
2
3
4
5
6
Typical Applications
•
High Availability Systems
•
Electronic Circuit Breaker
•
12 V Distributed Architecture
ORDERING INFORMATION
Device
NIS5102QP1HT1
(Latchoff)
Package
Shipping
†
NIS5102QP1HT1G 12 Pin PLLP 1500/Tape & Reel
(Latchoff)
(Pb-Free)
NIS5102QP2HT1
(Auto-Retry)
9x9 mm 1500/Tape & Reel
12 Pin PLLP
NIS5102QP2HT1G 12 Pin PLLP 1500/Tape & Reel
(Auto-Retry)
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2008
1
February, 2008 - Rev. 8
Î
ÎÎ
ÎÎ
ÎÎ
= 1 or 2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free
9x9 mm 1500/Tape & Reel
12 Pin PLLP
Publication Order Number:
NIS5102/D
NIS5102
V
CC
13
C
charge
5
Voltage
Regulator
Charge
Pump
Current
Limit
10, 11, 12
Source
Thermal
Shutdown
2
UVLO
Undervoltage
Lockout
6 Current Limit
7 Power Good
1
OVLO
Common
Shutdown
Overvoltage
Shutdown
Enable/
Timer
Power
Good
4 GND
3
Enable/Timer
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin
1
Function
OVLO
Description
The overvoltage shutdown point is programmed by a resistor from this pin to the V
CC
supply. When
tied together with other devices, this pin also communicates a shutdown state due to undervoltage
and overtemperature reasons. All devices connected will simultaneously shutdown. Startup for this
condition may be simultaneous or sequenced.
A resistor from V
CC
to the UVLO pin adjusts the voltage at which the device will turn on.
A high level signal on this pin allows the device to begin operation. Connection of a capacitor will
delay turn on for timing purposes. A low input signal inhibits the operation, and communicates to any
other paralleled devices (via the OVLO pin) to shutdown. This signal can also be used to reset the
thermal latch.
Negative input voltage to the device. This is used as the internal reference for the IC.
An external capacitor is required from this pin to the source pin. This is the storage capacitor for the
internal charge pump. A small internal capacitor is included for noise filtering.
A resistor (R
LIMIT
) tied from this pin to the source pin sets the current limit level.
A high impedance signal on this pin indicates that the power device is conducting.
-
Source of power FET, which is also the switching node for the load.
Positive input voltage to the device.
2
3
UVLO
Enable/Timer
4
5
6
7
8, 9
10, 11, 12
13
Ground
C
charge
I
LIMIT
Power Good
No Connection
Source
V
CC
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2
NIS5102
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
Rating
Input Voltage, Operating, Steady-State (Input + to Input -)
Input Voltage, Operating, Transient (Input + to Input -), 1 second
Drain Voltage, Operating, Steady-State (Drain to Input -)
Drain Voltage, Operating, Transient (Drain to Input -), 1 second
Drain Current, Peak
Continuous Current (T
A
= 25°C, 0.5 in
2
pad)
Voltage on Power Good Pin (Pin 7)
Thermal Resistance, Junction-to-Air
0.5 in
2
Copper
1 in
2
Copper
Thermal Resistance, Junction-to-Lead
Power Dissipation (T
A
= 25°C, 0.5 in
2
pad)
Operating Temperature Range (Note 1)
Non-Operating Temperature Range
Lead Temperature, Soldering (10 Sec)
Symbol
V
in
V
in
V
DD
V
DD
I
Dpk
I
Davg
V
max7
Q
JA
76.5
41.2
Q
JL
P
max
T
J
T
J
T
L
3.2
1.4
-40 to 175
-55 to 175
235
Value
-0.3 to 18
-0.3 to 25
-0.3 to 18
-0.3 to 25
20
10
20
Unit
V
V
V
V
A
A
V
°C/W
°C/W
°C/W
W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as
specified.
ELECTRICAL CHARACTERISTICS
(V
CC
= 12 V, R
LIMIT
= 36
W,
C
Charge
= 100 pF, T
J
= 25°C unless otherwise noted.)
Characteristic
POWER FET
Delay Time (Enable High to I
S
= 100 mA)
Charging Time (I
S
= 100 mA to I
S
= 5.0 A, R
LIMIT
= 36
W)
ON Resistance (V
CC
= 12 V, I
S
= 5.0 A) (Note 2)
Zero Gate Voltage Drain Current
(V
DS
= 12 V
dc
, V
GS
= 0 V
dc
)
Zero Gate Voltage Drain Current
(V
DS
= 18 V
dc
, V
GS
= 0 V
dc
)
Output Capacitance (V
DS
= 12 V
dc
, V
GS
= 0 V
dc
, f = 10 kHz)
THERMAL LIMIT
Shutdown Temperature (Note 3)
Hysteresis (Note 3)
OVER/UNDERVOLTAGE
UVLO Turn-on (Input + Increasing, Rext
UVLO
= 620 k)
UVLO Hysteresis (Input + Decreasing, Rext
UVLO
= 620 k)
OVLO Turn-off (Input + Increasing, Rext
UVLO
= 620 k)
OVLO Hysteresis (Input + Decreasing, Rext
UVLO
= 620 k)
PARALLEL SHUTDOWN
(Alternate Function on OVLO Pin)
Device Fan-out (Minimum External Resistor Value = 2.0 kW (Note 3)
Shutdown Voltage Threshold (OVLO Pin)
Shutdown State Output Voltage (Isink = 2.0 mA)
2. Pulse Test: Pulse width 300
ms,
duty cycle 2%.
3. Verified by design.
N
fan
V
SD
V
low
-
0.6
-
-
0.8
0.3
4.0
-
0.4
Devices
V
V
V
on
V
hyst
V
off
V
hyst
10.05
0.45
14.0
0.6
11.15
0.62
16.4
0.78
12.30
0.75
19.0
1.0
V
V
V
V
T
SD
T
hyst
125
-
135
40
145
-
°C
°C
T
dly
t
chg
R
DSon
I
DSS1
I
DSS2
-
-
-
-
-
-
-
2.0
1.0
10
-
-
-
-
-
13
10
100
-
ms
ms
mW
mA
mA
pF
Symbol
Min
Typ
Max
Unit
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3
NIS5102
ELECTRICAL CHARACTERISTICS
(continued)
(V
CC
= 12 V, R
LIMIT
= 36
W,
C
Charge
= 100 pF, T
J
= 25°C unless otherwise noted.)
Characteristic
CURRENT LIMIT
Current Limit (Short Circuit, R
LIMIT
= 36
W)
Current Limit (Overload, R
LIMIT
= 36
W)
(Note 3)
ENABLE/TIMER
Enable Voltage (Turn-On)
Enable Voltage (Turn-Off)
Charging Current (Into External Capacitor)
Turn-on Delay (Time from Enable High to I
source
= 100 mA)
CHARGE PUMP
C
Charge
(Voltage on Pin 5 with Respect to Ground)
V
CC
= 18 Vdc
POWER GOOD
Power Good
→
High Z Signal when FET is Fully Enhanced
Low Z State Output Voltage (I
Sink
= 2 mA)
Leakage Current (Vpin7 = 12 V, High Z State)
Power Good Delay
(Time from Power FET is Fully Enhanced to Power Good FET Changing State)
TOTAL DEVICE
Bias Current (Operational, V
CC
= 12 V)
Bias Current (Non-operational, V
CC
= 7 V))
Minimum Operating Voltage
I
Bias
I
Bias
Vcc
min
-
-
-
1.3
400
8.5
2.0
700
9.0
mA
mA
V
-
Vpin7
I
Leak
t
pwrgood
-
-
-
-
-
230
2.0
15
-
300
10
-
-
mV
mA
ms
V
Ccharge
-
-
18
26
-
-
V
V
V
ENon
V
ENoff
I
Charge
t
delay
2.2
-
65
-
-
-
77
2.2
-
1.6
88
-
V
V
mA
ms
I
LIM1
I
LIM2
3.8
7.0
4.8
7.8
5.8
8.6
A
A
Symbol
Min
Typ
Max
Unit
Output Current
Source Voltage
Enable/Timer
Threshold
Input
Figure 2. Timing Diagram for External Enabled Delay
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4
NIS5102
TYPICAL PERFORMANCE CURVES
(T
A
= 25°C unless otherwise noted)
14
13
UVLO TRIP POINT (V)
12
11
Turn-off
10
9
8
200
Turn-on
OVLO TRIP POINT (V)
19
18
17
16
15
14
13
12
11
10
300
400
500
600
700
800
900
1000
9
100
200
300
400
500
600
700
800
900 1000
Turn-on
Turn-off
R
UVLO
(kW)
R
OVLO
(kW)
Figure 3. UVLO Adjustment
100
12
10
Overload
CURRENT (A)
10
I
Limit
(A)
Figure 4. OVLO Adjustment
Overload
8
6
4
2
Short Circuit
1
Short Circuit
0.1
10
0
100
R
ILmit
(W)
1000
0
10
20
30
40
50
60
70
80
90
T
J
, JUNCTION TEMPERATURE, (°C)
Figure 5. Current Limit Adjustment
Figure 6. Current Limit vs. Temperature for
182W
105
10
CASE TEMPERATURE,
°C
Vin = 12 V
Rext_ILimit = 100
W
95
85
75
Device Reaching
Thermal Shutdown
di/dt (A/ms)
1
1/4 sq in copper area
65
1 sq in copper area
55
45
35
2 sq in copper area
0.1
0.01
10
25
100
1000
10000
LOAD CAPACITANCE (mF)
1.0
3.0
5.0
7.0
9.0
11
13
CONTINUOUS CURRENT, A
Figure 7. Load Capacitance vs. Output di/dt
Figure 8. Continuous Current vs. Case Temperature
(Test performed on a double-sided copper board, 1 oz)
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