DATASHEET
ISL6262
Two-Phase Core Regulator for IMVP-6 Mobile CPUs
The ISL6262 is a two-phase buck converter regulator
implementing Intel® IMVP-6 protocol, with embedded gate
drivers. The two-phase buck converter uses two interleaved
channels to effectively double the output voltage ripple
frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL6262 is R
3
Technology™, Intersil’s
Robust Ripple Regulator modulator. Compared with the
traditional multiphase buck regulator, the R
3
Technology™
has the fastest transient response. This is due to the R
3
modulator commanding variable switching frequency during
a load transient.
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6262 supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions and maximizes the efficiency
via automatically enabling different phase operation modes.
At heavy load operation of the active mode, the regulator
commands the two phase continuous conduction mode
(CCM) operation. While the PSI# is asserted at the medium
load in the active mode, the ISL6262 smoothly disables one
phase and operates in a one-phase CCM. When the CPU
enters deeper sleep mode, the ISL6262 enables diode
emulation to maximize the efficiency at the light load.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
A 0.5% system accuracy of the core output voltage over
temperature is achieved by the ISL6262.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
FN9199
Rev 2.00
May 15, 2006
Features
• Precision Two-phase CORE Voltage Regulator
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change on-the-fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
ISL6262CRZ
(Note)
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6262CRZ-T ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262IRZ
(Note)
ISL6262IRZ
-40 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
-40 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6262IRZ-T ISL6262IRZ
(Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN9199 Rev 2.00
May 15, 2006
Page 1 of 27
ISL6262
Pinout
ISL6262 (7x7 QFN)
TOP VIEW
DPRSLPVR
DPRSTP#
CLK_EN#
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
38
48
PGOOD
PSI#
PGD_IN
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
1
2
3
4
5
6
7
8
9
47
46
45
44
43
42
41
40
39
VID0
37
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
24
ISEN1
3V3
GND PAD
(BOTTOM)
COMP 10
FB 11
FB2 12
13
VDIFF
14
VSEN
15
RTN
16
DROOP
17
DFB
18
VO
19
VSUM
20
VIN
21
GND
22
VDD
23
ISEN2
FN9199 Rev 2.00
May 15, 2006
Page 2 of 27
ISL6262
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . . -0.3 -+7V
Thermal Information
Thermal Resistance (Typical)
JA
°C/W
JC
°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C
Ambient Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 100°C
Junction Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
INPUT POWER SUPPLY
+5V Supply Current
V
DD
= 5V, T
A
= -40°C to 100°C, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VDD
VR_ON = 3.3V
VR_ON = 0V
-
-
-
-
-
3.9
3.1
-
-
-
4.35
4.1
3.6
1
1
1
4.5
-
mA
µA
µA
µA
V
V
+3.3V Supply Current
Battery Supply Current at VIN pin
POR (Power-On Reset) Threshold
I
3V3
I
VIN
POR
r
POR
f
No load on CLK_EN#
VR_ON = 0V, VIN = 25V,
V
DD
Rising
V
DD
Falling
SYSTEM AND REFERENCES
System Accuracy
%Error
(V
cc_core
)
ISL6262CRZ
No load, closed loop, active mode,
T
A
= 0°C to 100°C, VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
%Error
(V
cc_core
)
ISL6262IRZ
RBIAS Voltage
Boot Voltage
Maximum Output Voltage
R
RBIAS
V
BOOT
V
CC_CORE
(max)
V
CC_CORE
(min)
VID Off State
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
f
SW
R
FSET
= 3.9k, 2 channel operation,
V
comp
= 2V
-
200
300
-
-
500
kHz
kHz
VID = [0000000]
VID = [1100000]
VID = [1111111]
T
A
= -40°C to 100°C, VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
R
RBIAS
= 147k
-0.5
-8
-15
-0.8
-10
-18
1.45
1.188
-
-
-
-
-
-
-
-
-
1.47
1.2
1.5
0.3
0
0.5
8
15
0.8
10
18
1.49
1.212
-
-
-
%
mV
mV
%
mV
mV
V
V
V
V
V
FN9199 Rev 2.00
May 15, 2006
Page 3 of 27
ISL6262
Electrical Specifications
PARAMETER
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
ISEN
Imbalance Voltage
Input Bias Current
SOFT-START CURRENT
Soft-Start Current
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
UGATE Source Current
UGATE Sink Resistance
UGATE Sink Current
LGATE Source Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
UGATE to PHASE Resistance
R
SRC(UGATE)
I
SRC(UGATE)
R
SNK(UGATE)
I
SNK(UGATE)
R
SRC(LGATE)
I
SRC(LGATE)
R
SNK(LGATE)
I
SNK(LGATE)
R
p(UGATE)
500mA Source Current
V
UGATE_PHASE
= 2.5V
500mA Sink Current
V
UGATE_PHASE
= 2.5V
500mA Source Current
V
LGATE
= 2.5V
500mA Sink Current
V
LGATE
= 2.5V
-
-
-
-
-
-
-
-
-
1
2
1
2
1
2
0.5
4
1.1
1.5
-
1.5
-
1.5
-
0.9
-
-
A
A
A
A
k
I
SS
I
GV
I
C4
I
C4EA
I
C4EB
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-47
±170
-47
35
170
-41
±200
-41
41
200
-35
±230
-35
47
230
µA
µA
µA
µA
µA
-
-
-
20
1
-
mV
nA
A
V0
GBW
SR
I
IN(FB)
C
L
= 20pF
C
L
= 20pF
-0.3
-
-
-
-
-
90
18
5
10
0.3
-
-
-
150
mV
dB
MHz
V/µs
nA
V
DD
= 5V, T
A
= -40°C to 100°C, Unless Otherwise Specified.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
GATE DRIVER SWITCHING TIMING
(refer to timing diagram)
UGATE Turn-On Propagation Delay
t
PDHU
ISL6262CRZ
t
PDHU
ISL6262IRZ
LGATE Turn-On Propagation Delay
t
PDHL
ISL6262CRZ
t
PDHL
ISL6262IRZ
BOOTSTRAP DIODE
Forward Voltage
Leakage
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
PGOOD Leakage Current
V
OL
I
OH
I
PGOOD
= 4mA
P
GOOD
= 3.3V
-
-1
0.11
-
0.4
1
V
µA
V
DDP
= 5V, Forward Bias Current = 2mA
V
R
= 16V
0.43
-
0.58
-
0.72
1
V
µA
T
A
= -10°C to 100°C
PV
CC
= 5V, Outputs Unloaded
PV
CC
= 5V, Outputs Unloaded
7
15
30
ns
T
A
= -10°C to 100°C
PV
CC
= 5V, Outputs Unloaded
PV
CC
= 5V, Outputs Unloaded
20
30
44
ns
18
30
44
ns
5
15
30
ns
FN9199 Rev 2.00
May 15, 2006
Page 4 of 27
ISL6262
Electrical Specifications
PARAMETER
PGOOD Delay
V
DD
= 5V, T
A
= -40°C to 100°C, Unless Otherwise Specified.
(Continued)
SYMBOL
t
pgd
ISL6262CRZ
t
pgd
ISL6262IRZ
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
Current Imbalance Threshold
Undervoltage Threshold
(VDIFF-SOFT)
LOGIC INPUTS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VR_ON, DPRSLPVR and PGD_IN
Input High
Leakage Current of VR_ON and
PGD_IN
Leakage Current of DPRSLPVR
V
IL
V
IH
I
IL
I
IH
I
IL_DPRSLP
I
IH_DPRSLP
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
Leakage Current of DAC(VID0-
VID6), PSI# and DPRSTP#
THERMAL MONITOR
NTC Source Current
Over-Temperature Threshold
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
V
OH
V
OL
3V3 = 3.3V, I = -4mA
I
CLK_EN#
= 4mA
2.9
-
3.1
0.18
-
0.4
V
V
R
TT
NTC = 1.3 V
V(NTC) falling
I = 20mA
53
1.165
-
60
1.18
5
68
1.205
9
µA
V
V
IL
V
IH
I
IL
I
IH
Logic input is low
Logic input is high at 1V
Logic input is low
Logic input is high at 3.3V
DPRSLPVR input is low
DPRSLPVR input is high at 3.3V
-
2.3
-1
-
-1
-
-
0.7
-1
-
-
-
0
0
0
0.45
-
-
0
0.45
1
-
-
1
-
1
0.3
-
-
1
V
V
µA
µA
µA
µA
V
V
µA
µA
UV
f
O
VH
O
VHS
V
O
rising above setpoint > 1ms
V
O
rising above setpoint > 0.5µs
I(Rbias) = 10µA
DROOP rising above OCSET > 120µs
Difference between ISEN1 and ISEN2 > 1ms
V
O
falling below setpoint for > 1ms
160
1.675
9.8
-3.5
-
-365
200
1.7
10
-
7.5
-300
240
1.725
10.2
3.5
-
-240
mV
V
µA
mV
mV
mV
TEST CONDITIONS
T
A
= -10°C to 100°C
CLK_EN# Low to PGOOD High
CLK_EN# Low to PGOOD High
MIN
5.5
TYP
6.8
MAX
8.1
UNITS
ms
5.3
6.8
8.1
ms
FN9199 Rev 2.00
May 15, 2006
Page 5 of 27
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