MB9B610T Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B610T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
2
such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN, Ethernet-MAC).
The products which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family PERIPHERAL
MANUAL".
®
®
Features
32-bit ARM Cortex -M3 Core
Processor version: r2p1
Up to 144 MHz Frequency Operation
Memory Protection Unit (MPU): improves the reliability of an
embedded system
®
®
External Bus Interface
Supports SRAM, NOR and NAND Flash device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY input
USB Interface (Max 2 channels)
USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock or Ethernet clock can be
generated by multiplication of Main clock.
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
Up to 1 Mbyte
Built-in Flash Accelerator System with 16 Kbyte trace buffer
memory
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at the
operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
[USB device]
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint
Security function for code protection
[SRAM]
This Series contain a total of up to 128 Kbyte on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
0 is control transfer
EndPoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
EndPoint 3 - 5 can be selected Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 is comprised Double Buffer
• EndPoint 0, 2 to 5:64 bytes
• EndPoint 1: 256 bytes
[USB host]
USB2.0 Full/Low speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
SRAM0: Up to 64 Kbyte
SRAM1: Up to 64 Kbyte
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-04677 Rev.*C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB9B610T Series
Ethernet - MAC (Max 2 channels)
Compliant with IEEE802.3 specification
10 Mbps / 100 Mbps data transfer rates supported
MII/RMII for external PHY device supported.
MII:
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
2
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
Max 1 channel
RMII: Max 2 channels
Full-Duplex and Half-Duplex mode supported.
Wake-ON-LAN supported
Built-in dedicated descriptor-system DMAC
Built-in 2 Kbyte Transmit FIFO and 2 Kbyte Receive FIFO.
Compliant IEEE1558-2008 (PTP)
Multi-function Serial Interface (Max 8 channels)
4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 32 channels)
[12-bit A/D Converter]
Successive Approximation Register type
Built-in 3units
Conversion time: 1.0 μs@5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
Various error detect functions available (parity errors, framing
errors, and overrun errors)
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as I/O ports when they are not used
for external bus or peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated.
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 154 fast I/O Ports@176pin Package
Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
Various error detect functions available (parity errors, framing
errors, and overrun errors)
Document Number: 002-04677 Rev.*C
Page 2 of 134
MB9B610T Series
Multi-function Timer (Max 3 units)
The Multi-function timer is composed of the following blocks.
External Interrupt Controller Unit
Up to 32 external interrupt input pin
Include one non-maskable interrupt(NMI)
Watch dog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP mode.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 3 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
Main Clock:
Sub Clock:
High-speed internal CR Clock:
Low-speed internal CR Clock:
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
4 MHz to 50 MHz
32.768 kHz
4 MHz
100 kHz
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from power saving
mode.
Interval timer: up to 64 s (Max)@ Sub Clock: 32.768 kHz
Document Number: 002-04677 Rev.*C
Page 3 of 134
MB9B610T Series
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Power Supply
Four Power Supplies
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
Wide range voltage VCC = 2.7 V to 5.5 V
USBVCC0
= 3.0 V to 3.6 V: for USB ch.0 I/O voltage,
when USB ch.0 is used.
= 2.7 V to 5.5 V: when GPIO is used.
= 3.0 V to 3.6 V: for USB ch.1 I/O voltage,
when USB ch.1 is used.
= 2.7 V to 5.5 V: when GPIO is used.
= 3.0 V to 5.5 V: for Ethernet I/O voltage,
when Ethernet is used.
= 2.7 V to 5.5 V: when GPIO is used.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-power Mode
Three power saving modes supported.
USBVCC1
ETHVCC
SLEEP
TIMER
STOP
Document Number: 002-04677 Rev.*C
Page 4 of 134
MB9B610T Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 52
6. Handling Precautions ..................................................................................................................................................... 58
6.1
Precautions for Product Design ................................................................................................................................... 58
6.2
Precautions for Package Mounting .............................................................................................................................. 59
6.3
Precautions for Use Environment ................................................................................................................................ 60
7. Handling Devices ............................................................................................................................................................ 61
8. Block Diagram ................................................................................................................................................................. 63
9. Memory Size .................................................................................................................................................................... 64
10. Memory Map .................................................................................................................................................................... 64
11. Pin Status in Each CPU State ........................................................................................................................................ 67
12. Electrical Characteristics ............................................................................................................................................... 72
12.1 Absolute Maximum Ratings ......................................................................................................................................... 72
12.2 Recommended Operating Conditions.......................................................................................................................... 74
12.3 DC Characteristics....................................................................................................................................................... 76
12.3.1 Current Rating .............................................................................................................................................................. 76
12.3.2 Pin Characteristics ....................................................................................................................................................... 78
12.4 AC Characteristics ....................................................................................................................................................... 80
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 80
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 81
12.4.3 Internal CR Oscillation Characteristics ......................................................................................................................... 81
12.4.4 Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input of PLL) .................... 82
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 82
12.4.6 Reset Input Characteristics .......................................................................................................................................... 83
12.4.7 Power-on Reset Timing................................................................................................................................................ 83
12.4.8 External Bus Timing ..................................................................................................................................................... 84
12.4.9 Base Timer Input Timing .............................................................................................................................................. 94
12.4.10 CSIO/UART Timing .................................................................................................................................................. 95
12.4.11 External Input Timing .............................................................................................................................................. 103
12.4.12 Quadrature Position/Revolution Counter timing ...................................................................................................... 104
2
12.4.13 I C Timing ............................................................................................................................................................... 106
12.4.14 ETM Timing ............................................................................................................................................................ 107
12.4.15 JTAG Timing ........................................................................................................................................................... 108
12.4.16 Ethernet-MAC Timing ............................................................................................................................................. 109
12.5 12-bit A/D Converter .................................................................................................................................................. 114
12.6 USB characteristics ................................................................................................................................................... 117
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 121
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 121
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 121
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 122
12.8.1 Write / Erase time....................................................................................................................................................... 122
12.8.2 Write cycles and data hold time ................................................................................................................................. 122
12.9 Return Time from Low-Power Consumption Mode .................................................................................................... 123
12.9.1 Return Factor: Interrupt .............................................................................................................................................. 123
Document Number: 002-04677 Rev.*C
Page 5 of 134
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