74HC138; 74HCT138
Rev. 7 — 26 March 2018
3-to-8 line decoder/demultiplexer; inverting
Product data sheet
1
General description
The 74HC138; 74HCT138 decodes three binary weighted address inputs
(A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three
enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW
and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32
(5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used
as an eight output demultiplexer by using one of the active LOW enable inputs as the
data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2
Features and benefits
•
Complies with JEDEC standard no. 7A
•
Input levels:
–
For 74HC138: CMOS level
–
For 74HCT138: TTL level
•
Demultiplexing capability
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Active LOW mutually exclusive outputs
•
ESD protection:
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
•
Multiple package options
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Nexperia
3-to-8 line decoder/demultiplexer; inverting
74HC138; 74HCT138
3
Ordering information
Package
Temperature range Name
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO16
SSOP16
TSSOP16
Table 1. Ordering information
Type number
74HC138D
74HCT138D
74HC138DB
74HCT138DB
74HC138PW
74HCT138PW
74HC138BQ
74HCT138BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5 × 3.5 × 0.85 mm
4
Functional diagram
Y0
1
2
3
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
mna372
15
14
13
12
11
10
9
7
1
2
3
E1
E2
E3
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
mna370
15
14
13
12
11
10
9
7
4
5
6
Figure 1. Logic symbol
Figure 2. Functional diagram
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 26 March 2018
2 / 19
Nexperia
3-to-8 line decoder/demultiplexer; inverting
74HC138; 74HCT138
Y7
Y6
Y5
A2
A1
A0
Y4
E1
Y3
E2
Y2
E3
Y1
Y0
001aae059
Figure 3. Logic diagram
5
Pinning information
5.1 Pinning
74HC138
74HCT138
terminal 1
index area
A1
2
3
4
5
6
7
8
GND
Y6
9
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
A0
1
74HC138
74HCT138
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
aaa-028342
A2
E1
E2
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
74HC138
74HCT138
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
aaa-028343
E3
Y7
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
aaa-028344
Transparent top view
(1) This is not a supply pin. The
substrate is attached to this pad using
conductive die attach material. There is
no electrical or mechanical requirement
to solder this pad.However, if it is
soldered, the solder land should remain
floating or be connected to GND.
Figure 4. Pin configuration SOT109-1 Figure 5. Pin configuration SOT338-1 Figure 6. Pin configuration SOT763-1
(SO16)
(SSOP16) and SOT403-1 (TSSOP16) (DHVQFN16)
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 26 March 2018
3 / 19
Nexperia
3-to-8 line decoder/demultiplexer; inverting
74HC138; 74HCT138
5.2 Pin description
Table 2. Pin description
Symbol
A0, A1, A2
E1, E2
E3
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
GND
V
CC
Pin
1, 2, 3
4, 5
6
15, 14, 13, 12, 11, 10, 9, 7
8
16
Description
address input
enable input (active LOW)
enable input (active HIGH)
output (active LOW)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Control
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
Input
A2
X
A1
X
A0
X
Output
Y7
H
Y6
H
Y5
H
Y4
H
Y3
H
Y2
H
Y1
H
Y0
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 26 March 2018
4 / 19
Nexperia
3-to-8 line decoder/demultiplexer; inverting
74HC138; 74HCT138
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
supply voltage
input clamping current
output clamping current
output current
quiescent supply current
ground current
storage temperature
total power dissipation
[1]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
Min
-0.5
-
-
-
-
-50
-65
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
[1] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 °C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN16 packages: P
tot
derates linearly with 4.5 mW/K above 60 °C.
8
Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-40
-
-
-
74HC138
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
-40
-
-
-
74HCT138
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 26 March 2018
5 / 19
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