CY8C29466, CY8C29666
Automotive – Extended Temperature
PSoC
®
Programmable System-on-Chip
Features
■
■
■
AEC qualified
Powerful Harvard-Architecture processor
❐
M8C processor speeds up to 12 MHz
❐
Two 8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 4.75 V to 5.25 V
❐
Extended temperature range: –40 °C to +125 °C
Advanced peripherals (PSoC
®
blocks)
❐
12 Rail-to-Rail analog PSoC blocks provide:
• Up to 14-Bit analog-to-digital converters (ADCs)
• Up to 9-Bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGA)
• Programmable filters and comparators
❐
16 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Up to four full-duplex or eight half-duplex UARTs
• Multiple SPI masters or slaves
• Connectable to all general purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
Precision, programmable clocking
❐
Internal ±4% 24 MHz oscillator
❐
High accuracy 24 MHz with optional 32.768 kHz crystal
and phase locked loop (PLL)
❐
Optional external oscillator, up to 24 MHz
❐
Internal low speed, low power oscillator for Watchdog and
Sleep functionality
Flexible on-chip memory
❐
32K bytes flash program storage,
100 erase/write cycles
❐
2K bytes SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Programmable pin configurations
❐
25 mA sink, 10 mA drive on all GPIOs
❐
Pull up, pull down, high Z, strong, or open drain drive modes
on all GPIO
[1]
❐
Up to 12 analog inputs on GPIO
❐
Four 30 mA analog outputs on GPIO
❐
Configurable interrupt on all GPIOs
Additional system resources
2
❐
I C™ master, slave, or multi-master operation up to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low voltage detection (LVD)
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full featured in-circuit emulator (ICE) and
programmer
❐
Full speed emulation
❐
Complex breakpoint structure
❐
128 K bytes trace memory
❐
Complex events
❐
C Compilers, assembler, and linker
■
■
Logic Block Diagram
PSoC
CORE
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Interrupt
Controller
SROM
■
Global Analog Interconnect
Flash 32K
Sleep and
Watchdog
CPU Core (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block Array
Analog
Block Array
Analog
Input
Muxing
■
Digital
Clocks
Two
Multiply
Accums.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the
PSoC Technical Reference Manual
for more details
Cypress Semiconductor Corporation
Document Number: 38-12026 Rev. *O
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 1, 2017
CY8C29466, CY8C29666
Contents
PSoC Functional Overview .............................................. 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
28-pin Part Pinout ........................................................ 9
48-pin Part Pinout ...................................................... 10
Registers ......................................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Operating Temperature ............................................. 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 22
Packaging Information ................................................... 29
Thermal Impedances ................................................. 30
Capacitance on Crystal Pins ..................................... 30
Solder Reflow Specifications ..................................... 30
Development Tool Selection ......................................... 31
Software .................................................................... 31
Development Kits ...................................................... 31
Evaluation Tools ........................................................ 31
Device Programmers ................................................. 31
Accessories (Emulation and Programming) .............. 32
Ordering Information ...................................................... 32
Ordering Code Definitions ......................................... 32
Reference Information ................................................... 33
Acronyms Used ......................................................... 33
Units of Measure ....................................................... 33
Numeric Naming ........................................................ 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC® Solutions ...................................................... 36
Cypress Developer Community ................................. 36
Technical Support ..................................................... 36
Document Number: 38-12026 Rev. *O
Page 2 of 36
CY8C29466, CY8C29666
PSoC Functional Overview
The PSoC programmable system-on-chip family consists of
many devices with on-chip controllers. These devices are
designed to replace multiple traditional microcontroller unit
(MCU)-based system components with one, low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, as well as programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, as illustrated in the
Logic Block Diagram
on page 1,
is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. The PSoC CY8C29x66 family can
have up to six I/O ports that connect to the global digital and
analog interconnects, providing access to 16 digital blocks and
12 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU utilizes an interrupt controller with 25
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep Timer and Watch Dog Timer (WDT).
Memory includes 32K of Flash for program storage and 2K of
SRAM for data storage. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±4% over temperature and voltage. A low power 32 kHz internal
low speed oscillator (ILO) is provided for the Sleep Timer and
WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate
24 MHz system clock using a PLL. The clocks, together with
programmable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into the
PSoC device.
PSoC GPIOs provide connection to the CPU, digital resources,
and analog resources of the device. Each pin’s drive mode may
be selected from eight options, allowing great flexibility in
external interfacing. Every pin also has the capability to generate
a system interrupt.
■
■
■
■
■
■
■
■
■
■
PWMs (8- and 16-bit)
PWMs with Dead Band (8- and 16-bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
Full or Half-Duplex 8-bit UART with selectable parity (up to 4
Full-Duplex or 8 Half-Duplex)
SPI master and slave (up to 8 total)
I
2
C master, slave, or multi-master
Cyclical Redundancy Checker/Generator (16 bit)
IrDA (up to 4)
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 1 on page 5.
Figure 1. Digital System Block Diagram
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
8
8
Row Input
Configuration
8
Row 1
DBB10
DBB11
DCB12
4
DCB13
4
8
Row Output
Configuration
Row Input
Configuration
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
Row Output
Configuration
Row Input
Configuration
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations include
those listed here.
Row 3
DBB30
DBB31
DCB32
4
DCB33
4
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12026 Rev. *O
Page 3 of 36
CY8C29466, CY8C29666
The Analog System
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are as follows:
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
ADCs (up to 4, with 6- to 14-bit resolution, selectable as
Incremental, Delta-Sigma, and SAR)
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
Amplifiers (up to 4, with selectable gain up to 48x)
Instrumentation amplifiers (up to 2, with selectable gain up to
93x)
Comparators (up to 4, with 16 selectable thresholds)
DACs (up to 4, with 6- to 9-bit resolution)
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
High current output drivers (four with 30 mA drive as a PSoC
Core resource)
1.3 V reference (as a System Resource)
DTMF Dialer
Correlators
Peak Detectors
Many other topologies possible
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
ACB02
ASC12
ASD22
ACB03
ASD13
ASC23
Analog blocks are provided in columns of three, which includes
one Continuous Time (CT) and two Switched Capacitor (SC)
blocks, as shown in
Figure 2.
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12026 Rev. *O
Page 4 of 36
CY8C29466, CY8C29666
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are given below:
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
The I
2
C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR (Power On Reset) circuit
eliminates the need for a system supervisor.
An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Two multiply accumulates (MACs) provide fast 8-bit multiplier
with 32-bit accumulate to assist in both general math as well
as digital filters.
■
■
■
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog
blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet
is highlighted in
Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
[2]
CY8C27x43
CY8C24x94
CY8C24x23A
[2]
CY8C23x33
CY8C21x34
[2]
CY8C21x23
CY8C20x34
Digital
I/O
up to 64
up to 44
64
up to 24
up to
up to 28
16
up to 28
Digital
Rows
4
2
1
1
1
1
1
0
Digital
Blocks
16
8
4
4
4
4
4
0
Analog
Inputs
12
12
48
12
12
28
8
28
Analog
Outputs
4
4
2
2
2
0
0
0
Analog
Columns
4
4
2
2
2
2
2
0
Analog
Blocks
12
12
6
6
4
4
[3]
4
[3]
3
[3, 4]
SRAM
Size
2K
256 Bytes
1K
256 Bytes
256 Bytes
512 Bytes
256 Bytes
512 Bytes
Flash
Size
32K
16K
16K
4K
8K
8K
4K
8K
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality
.
4. Two analog blocks and one CapSense.
Document Number: 38-12026 Rev. *O
Page 5 of 36
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