74AHC30; 74AHCT30
8-input NAND gate
Rev. 03 — 26 June 2009
Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
N
For 74AHC30: CMOS level
N
For 74AHCT30: TTL level
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC30D
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
−40 °C
to +125
°C
DHVQFN14
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
4. Functional diagram
1
2
3
4
5
6
11
12
A
B
C
D
E
F
G
H
mna488
1
2
3
Y
8
4
5
6
11
12
&
8
mna489
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
B
C
D
Y
E
mna490
F
G
H
Fig 3.
Logic diagram
74AHC_AHCT30_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 June 2009
2 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
5. Pinning information
5.1 Pinning
74AHC30
74AHCT30
74AHC30
74AHCT30
A
B
C
D
E
F
GND
1
2
3
4
5
6
7
001aai162
terminal 1
index area
B
14 V
CC
13 n.c.
12 H
11 G
10 n.c.
9
8
n.c.
Y
F
6
C
D
E
2
3
4
5
14 V
CC
13 n.c.
12 H
11 G
10 n.c.
9
n.c.
Y
8
GND
(1)
7
GND
1
A
001aak237
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
A
B
C
D
E
F
GND
Y
n.c.
n.c.
G
H
n.c.
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
not connected
data input
data input
not connected
supply voltage
74AHC_AHCT30_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 June 2009
3 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
6. Functional description
Table 3.
Input
A
L
X
X
X
X
X
X
X
H
[1]
Function table
[1]
Output
B
X
L
X
X
X
X
X
X
H
C
X
X
L
X
X
X
X
X
H
D
X
X
X
L
X
X
X
X
H
E
X
X
X
X
L
X
X
X
H
F
X
X
X
X
X
L
X
X
H
G
X
X
X
X
X
X
L
X
H
H
X
X
X
X
X
X
X
L
H
Y
H
H
H
H
H
H
H
H
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT30_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 June 2009
4 of 14
NXP Semiconductors
74AHC30; 74AHCT30
8-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
Min
2.0
0
0
−40
-
-
74AHC30
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Min
4.5
0
0
−40
-
-
74AHCT30
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC30
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
V
I
= V
CC
or GND
74AHC_AHCT30_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 June 2009
5 of 14
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