19-3826; Rev 1; 6/07
KIT
ATION
EVALU
BLE
AVAILA
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
Features
♦
Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit,
45Msps Tx DAC
♦
Ultra-Low Power
84.6mW at f
CLK
= 45MHz, Fast Mode
77.1mW at f
CLK
= 45MHz, Slow Mode
Low-Current Standby and Shutdown Modes
♦
Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim
♦
Excellent Dynamic Performance
SNR = 54.2dB at f
IN
= 5.5MHz (Rx ADC)
SFDR = 73.2dBc at f
OUT
= 2.2MHz (Tx DAC)
♦
Three 12-Bit, 1µs Aux-DACs
♦
10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data Averaging
♦
Excellent Gain/Phase Match
±0.03° Phase, ±0.01dB Gain (Rx ADC) at
f
IN
= 5.5MHz
♦
Multiplexed Parallel Digital I/O
♦
Serial-Interface Control
♦
Versatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx Disable
♦
Miniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
General Description
The MAX19707 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for power-sensitive com-
munication equipment. Optimized for high dynamic
performance at ultra-low power, the device integrates a
dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit,
45Msps transmit (Tx) DAC; three fast-settling 12-bit
aux-DAC channels for ancillary RF front-end control;
and a 10-bit, 333ksps housekeeping aux-ADC. The typ-
ical operating power in Tx-Rx FAST mode is 84.6mW at
a 45MHz clock frequency.
The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR
at f
IN
= 5.5MHz and f
CLK
= 45MHz. The analog I/Q
input amplifiers are fully differential and accept
1.024V
P-P
full-scale signals. Typical I/Q channel match-
ing is ±0.03° phase and ±0.01dB gain.
The Tx DACs feature 73.2dBc SFDR at f
OUT
= 2.2MHz
and f
CLK
= 45MHz. The analog I/Q full-scale output volt-
age is ±400mV differential. The Tx DAC common-mode
DC level is programmable from 0.71V to 1.05V. The I/Q
channel offset is programmable to optimize radio lineup
sideband/carrier suppresion. The typical I/Q channel
matching is ±0.01dB gain and ±0.07° phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
The MAX19707 operates on a single 2.7V to 3.3V ana-
log supply and 1.8V to 3.3V digital I/O supply. The
MAX19707 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The
Selector Guide
at the end of the
data sheet lists other pin-compatible versions in this
AFE family.
MAX19707
Pin Configuration
DAC3
ADC1
ADC2
V
DD
GND
V
DD
SCLK
DIN
T/R
TOP VIEW
DOUT
SHDN
24
23
22
21
20
19
18
17
16
36 35 34 33 32 31 30 29 28 27 26 25
CS
DAC2
DAC1
V
DD
IDN
IDP
GND
V
DD
QDN
QDP
REFIN
COM
REFN
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9 10 11 12
D9
D8
D7
D6
OV
DD
OGND
D5
D4
D3
D2
D1
D0
Applications
WiMAX CPEs
802.11a/b/g WLAN
VoIP Terminals
Portable Communication
Equipment
MAX19707
Ordering Information
PART*
MAX19707ETM
MAX19707ETM+
PIN-PACKAGE
48 Thin QFN-EP**
48 Thin QFN-EP**
PKG CODE
T4877-4
T4877-4
EXPOSED PADDLE (GND)
15
14
13
REFP
V
DD
IAP
IAN
GND
CLK
GND
V
DD
QAN
QAP
*All
devices are specified over the -40°C to +85°C operating
range.
**EP
= Exposed paddle.
+Denotes
lead-free package.
THIN QFN
Functional Diagram and Selector Guide appear at end of
data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
GND
V
DD
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
MAX19707
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND-0.3V to (VDD + 0.3V)D0–D9,
DOUT, T/R,
SHDN,
SCLK, DIN,
CS,
CLK to OGND .....................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN (derate 27.8mW/°C above +70°C) .....2.22W
Thermal Resistance
θ
JA ..................................................36°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
V
DD
OV
DD
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
f
CLK
= 45MHz, f
OUT
= 2.2MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
f
CLK
= 45MHz, f
OUT
= 2.2MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
V
DD
Supply Current
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
f
CLK
= 45MHz, f
IN
= 5.5MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
f
CLK
= 45MHz, f
IN
= 5.5MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
2.7
1.8
3.0
3.3
V
DD
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16.5
29.8
35
mA
28.2
34
25.7
2
_______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Standby mode: CLK = 0 or OV
DD
;
aux-DACs ON and at midscale,
aux-ADC ON
V
DD
Supply Current
Idle mode: f
CLK
= 45MHz; aux-DACs ON
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
DD
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): f
CLK
= 45MHz,
f
IN
= 5.5MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx), f
CLK
= 45MHz, f
OUT
= 2.2MHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OV
DD
; aux-DACs
ON and at midscale, aux-ADC ON
Idle mode: f
CLK
= 45MHz; aux-DACs ON
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
DD
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
PSRR
Offset error (V
DD
±5%)
Gain error (V
DD
±5%)
N
INL
DNL
Residual DC offset error
Include reference error
-5
-5.5
-0.15
10
±1.6
±0.7
±0.5
±1.0
±0.01
±13
±30
±0.4
±0.1
+5
+5.5
+0.15
Bits
LSB
LSB
%FS
%FS
dB
LSB
ppm/°C
LSB
%FS
MIN
TYP
3.2
MAX
5
mA
12.1
1
15
µA
UNITS
MAX19707
7.7
mA
OV
DD
Supply Current
485
µA
1
76
1
_______________________________________________________________________________________
3
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
MAX19707
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Rx ADC ANALOG INPUT
Input Differential Range
Input Common-Mode Voltage
Range
Input Impedance
Rx ADC CONVERSION RATE
Maximum Clock Frequency
Data Latency (Figure 3)
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
Third-Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
Aperture Delay
Overdrive Recovery Time
Rx ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Amplitude Matching
Phase Matching
f
INX,Y
= 5.5MHz at -0.5dBFS, f
INX,Y
= 1.8MHz
at -0.5dBFS (Note 4)
f
IN
= 5.5MHz at -0.5dBFS (Note 5)
f
IN
= 5.5MHz at -0.5dBFS (Note 5)
-90
±0.01
±0.03
dB
dB
Degrees
1.5x full-scale input
SNR
SINAD
SFDR
HD3
IMD
IM3
THD
f
IN
= 5.5MHz, f
CLK
= 45MHz
f
IN
= 22MHz, f
CLK
= 45MHz
f
IN
= 5.5MHz, f
CLK
= 45MHz
f
IN
= 22MHz, f
CLK
= 45MHz
f
IN
= 5.5MHz, f
CLK
= 45MHz
f
IN
= 22MHz, f
CLK
= 45MHz
f
IN
= 5.5MHz, f
CLK
= 45MHz
f
IN
= 22MHz, f
CLK
= 45MHz
f
1
= 1.8MHz,
-7dBFS;
f
2
= 1MHz, -7dBFS
f
1
= 1.8MHz, -7dBFS;
f
2
= 1MHz, -7dBFS
f
IN
= 5.5MHz, f
CLK
= 45MHz
f
IN
= 22MHz, f
CLK
= 45MHz
62.1
52.2
52.5
54.2
54.1
54.1
54
71.2
70.4
-78.1
-73.1
-68.6
-79.2
-68.4
-68.8
3.5
2
-61.5
dB
dB
dBc
dBc
dBc
dBc
dBc
ns
ns
f
CLK
(Note 2)
Channel I
Channel Q
5
5.5
45
MHz
Clock
Cycles
V
ID
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±0.512
V
DD
/ 2
120
5
V
V
kΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
_______________________________________________________________________________________
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Tx DAC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Residual DC Offset
Full-Scale Gain Error
Tx DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
In-Band Noise Density
Third-Order Intermodulation
Distortion
Glitch Impulse
Spurious-Free Dynamic Range to
Nyquist
Total Harmonic Distortion to
Nyquist
Signal-to-Noise Ratio to Nyquist
I-to-Q Output Isolation
Gain Mismatch Between DAC
Outputs
Phase Mismatch Between DAC
Outputs
Differential Output Impedance
Tx DAC ANALOG OUTPUT
Full-Scale Output Voltage
V
FS
Bits CM1 = 0, CM0 = 0 (default)
Output Common-Mode Voltage
V
COM
Bits CM1 = 0, CM0 = 1
Bits CM1 = 1, CM0 = 0
Bits CM1 = 1, CM0 = 1
1.0
±400
1.05
0.95
0.80
0.71
1.1
V
mV
SFDR
THD
SNR
f
CLK
= 45MHz, f
OUT
= 2.2MHz
f
CLK
= 45MHz, f
OUT
= 2.2MHz
f
CLK
= 45MHz, f
OUT
= 2.2MHz
f
OUTX,Y
= 2MHz, f
OUTX,Y
= 2.2MHz
Measured at DC
T
A
≥
+25°C
T
A
< +25°C
-0.3
-0.42
±0.07
800
60
f
CLK
N
D
IM3
(Note 2)
f
OUT
= 2.2MHz, f
CLK
= 45MHz
f
1
= 2MHz, f
2
= 2.2MHz
-130.6
80
10
73.2
-71
57.1
85
±0.01
+0.3
+0.42
-59
45
MHz
dBc/Hz
dBc
pV
•
s
dBc
dB
dB
dB
dB
Degrees
Ω
N
INL
DNL
V
OS
Guaranteed monotonic (Note 6)
T
A
≥
+25°C
T
A
< +25°C
Include reference error
(peak-to-peak error)
T
A
≥
+25°C
T
A
< +25°C
-1
-4
-4.5
-30
-40
10
±0.3
±0.2
±1
±1
+1
+4
+4.5
+30
+40
Bits
LSB
LSB
mV
mV
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19707
Tx DAC INTERCHANNEL CHARACTERISTICS
f
OUT
= 2.2MHz, f
CLK
= 45MHz
_______________________________________________________________________________________
5
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