SAF1562
Hi-Speed Universal Serial Bus PCI Host Controller
Rev. 3 — 19 June 2012
Product data sheet
1. General description
The SAF1562HL is a Peripheral Component Interconnect (PCI)-based, single-chip
Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host
Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface
(EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original
USB. The functional parts of the SAF1562HL are fully compliant with
Universal Serial Bus
Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a,
Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI
Local Bus Specification Rev. 2.2,
and
PCI Bus Power Management Interface Specification
Rev. 1.1.
The integrated high performance USB transceivers allow the SAF1562HL to handle all
Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and
low-speed (1.5 Mbit/s). The SAF1562HL provides two downstream ports, allowing
simultaneous connection of USB devices at different speeds.
The SAF1562HL is fully compatible with various operating system drivers, such as
Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP,
Windows 2000 and Red Hat Linux.
The SAF1562HL directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can
source 3.3 V. The PCI interface fully complies with
PCI Local Bus Specification Rev. 2.2.
The SAF1562HL is ideally suited for use in Hi-Speed USB mobile applications and
embedded solutions. The SAF1562HL uses a 12 MHz crystal.
2. Features and benefits
Complies with
Universal Serial Bus Specification Rev. 2.0
Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and
low-speed (1.5 Mbit/s)
Two Original USB OHCI cores comply with
Open Host Controller Interface
Specification for USB Rev. 1.0a
One Hi-Speed USB EHCI core complies with
Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0
Supports PCI 32-bit, 33 MHz interface compliant with
PCI Local Bus Specification
Rev. 2.2,
with support for D3
cold
standby and wake-up modes; all I/O pins are 3.3 V
standard
NXP Semiconductors
SAF1562
Hi-Speed Universal Serial Bus PCI Host Controller
Compliant with
PCI Bus Power Management Interface Specification Rev. 1.1
for all
hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3
hot
and D3
cold
CLKRUN support for mobile applications, such as internal notebook design
Configurable subsystem ID and subsystem vendor ID through external EEPROM
Digital and analog power separation for better Electro-Magnetic Interference (EMI) and
ElectroStatic Discharge (ESD) protection
Supports hot plug and play and remote wake-up of peripherals
Supports individual power switching and individual overcurrent protection for
downstream ports
Supports partial dynamic port-routing capability for downstream ports that allows
sharing of the same physical downstream ports between the Original USB Host
Controller and the Hi-Speed USB Host Controller
Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions
Supports dual power supply: PCI V
aux(3V3)
and V
CC
Operates at +3.3 V power supply input
Low power consumption
Qualified in accordance with AEC-Q100
Operating temperature range from
−40 °C
to +85
°C
Available in LQFP100 package
3. Applications
This NXP USB product can only be used in automotive applications. Inclusion or use of
the NXP USB products in other than automotive applications is not permitted and for your
company’s own risk. Your company agrees to full indemnify NXP for any damages
resulting from such inclusion or use.
4. Ordering information
Table 1.
Ordering information
Package
Name
SAF1562HL
LQFP100
Description
plastic low profile quad flat package; 100 leads; body 14
×
14
×
1.4 mm
Version
SOT407-1
Type number
SAF1562
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 19 June 2012
2 of 121
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Product data sheet
Rev. 3 — 19 June 2012
3 of 121
SAF1562
5. Block diagram
NXP Semiconductors
SCL
PME#
PCICLK
32 AD[31:0]
99
7
10, 12 to 15, 20 to 22,
26 to 31, 33, 34,
50 to 54, 56, 57,
59, 62, 63, 65 to 70
23, 35, 48, 60
REQ#
GNT#
IDSEL
32-bit, 33 MHz PCI bus
INTA#
FRAME#
DEVSEL#
IRDY#
CLKRUN#
PAR
PERR#
SERR#
TRDY#
STOP#
RST#
V
CC(I/O)
9
8
24
4
36
39
37
CONFIGURATION FUNCTION 0
42
47
44
45
38
41
5
11, 25, 40,
55, 71
POR
ATX1
REG1V8
V
I(VREG3V3)
18, 43, 58
VOLTAGE
REGULATOR
V
CC
DETECT
V
CC
core
ORIGINAL
USB ATX
Hi-SPEED
USB ATX
core
RESET_N
PORT ROUTER
CONFIGURATION FUNCTION 1
CONFIGURATION FUNCTION 2
RAM
RAM
CONFIGURATION SPACE
OHCI
(FUNCTION 0)
PCI SLAVE
PCI MASTER
96
SDA
97
77, 98, 100
V
CC(I/O)_AUX
GLOBAL CONTROL
PCI CORE
C/BE#[3:0]
VOLTAGE
REGULATOR
(V
aux
)
3
V
I(VAUX3V3)
SAF1562HL
2, 73
V
aux(1V8)
core
AUX1V8
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
OHCI
(FUNCTION 1)
EHCI
(FUNCTION 2)
RAM
81
RREF
Hi-Speed Universal Serial Bus PCI Host Controller
1, 17, 46,
61, 72, 80,
82, 84,
89, 91
GNDA
ATX2
ORIGINAL
USB ATX
Hi-SPEED
USB ATX
6, 19, 32,
49, 64, 76,
94, 95
GNDD
16
74
75
XTAL1
XTAL2
SAF1562
XOSC
PLL
86, 93
V
DDA_AUX
78
OC1_N
PWE1_N
79
83
DM1
85
DP1
87
OC2_N
PWE2_N
88
90
DM2
92
008aaa199
DP2
Fig 1.
Block diagram of SAF1562HL
NXP Semiconductors
SAF1562
Hi-Speed Universal Serial Bus PCI Host Controller
6. Pinning information
6.1 Pinning
100 V
CC(I/O)_AUX
98 V
CC(I/O)_AUX
77 V
CC(I/O)_AUX
93 V
DDA_AUX
86 V
DDA_AUX
88 PWE2_N
79 PWE1_N
87 OC2_N
78 OC1_N
95 GNDD
94 GNDD
GNDA
AUX1V8
V
I(VAUX3V3)
INTA#
RST#
GNDD
PCICLK
GNT#
REQ#
1
2
3
4
5
6
7
8
9
76 GNDD
91 GNDA
89 GNDA
80 GNDA
84 GNDA
82 GNDA
99 PME#
81 RREF
90 DM2
83 DM1
97 SDA
96 SCL
92 DP2
85 DP1
75 XTAL2
74 XTAL1
73 AUX1V8
72 GNDA
71 V
CC(I/O)
70 AD[0]
69 AD[1]
68 AD[2]
67 AD[3]
66 AD[4]
65 AD[5]
64 GNDD
AD[31] 10
V
CC(I/O)
11
AD[30] 12
AD[29] 13
AD[28] 14
AD[27] 15
V
I(VREG3V3)
16
GNDA 17
REG1V8 18
GNDD 19
AD[26] 20
AD[25] 21
AD[24] 22
C/BE#[3] 23
IDSEL 24
V
CC(I/O)
25
AD[23] 26
AD[22] 27
AD[21] 28
AD[20] 29
AD[19] 30
AD[18] 31
GNDD 32
AD[17] 33
AD[16] 34
C/BE#[2] 35
FRAME# 36
IRDY# 37
TRDY# 38
DEVSEL# 39
V
CC(I/O)
40
STOP# 41
CLKRUN# 42
REG1V8 43
PERR# 44
SERR# 45
GNDA 46
PAR 47
C/BE#[1] 48
GNDD 49
AD[15] 50
SAF1562HL
63 AD[6]
62 AD[7]
61 GNDA
60 C/BE#[0]
59 AD[8]
58 REG1V8
57 AD[9]
56 AD[10]
55 V
CC(I/O)
54 AD[11]
53 AD[12]
52 AD[13]
51 AD[14]
008aaa026
Fig 2.
Pin configuration for LQFP100
SAF1562
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 19 June 2012
4 of 121
NXP Semiconductors
SAF1562
Hi-Speed Universal Serial Bus PCI Host Controller
6.2 Pin description
Table 2.
Symbol
[1]
GNDA
AUX1V8
Pin description
Pin
1
2
Type
-
-
Description
analog ground
1.8 V auxiliary output voltage; only for voltage conditioning; cannot be
used to supply power to external components; connected to 100 nF
and 4.7
μF
capacitors
3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor
PCI interrupt
PCI pad; 3.3 V signaling; open-drain
RST#
5
I
PCI reset; used to bring PCI-specific registers, sequencers and
signals to a consistent state
3.3 V input pad; push-pull
GNDD
PCICLK
GNT#
REQ#
6
7
8
9
-
I
I/O
I/O
digital ground
PCI system clock (33 MHz)
PCI pad; 3.3 V signaling
PCI grant; indicates to the agent that access to the bus is granted
PCI pad; 3.3 V signaling
PCI request; indicates to the arbitrator that the agent wants to use the
bus
PCI pad; 3.3 V signaling
AD[31]
V
CC(I/O)
AD[30]
AD[29]
AD[28]
AD[27]
V
I(VREG3V3)
GNDA
REG1V8
10
11
12
13
14
15
16
17
18
I/O
-
I/O
I/O
I/O
I/O
-
-
-
bit 31 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
3.3 V supply voltage; used to power pads; add a 100 nF decoupling
capacitor
bit 30 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
bit 29 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
bit 28 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
bit 27 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
3.3 V regulator input voltage; add a 100 nF decoupling capacitor
analog ground
1.8 V regulator output voltage; only for voltage conditioning; cannot
be used to supply power to external components; connected to
100 nF and 4.7
μF
capacitors
digital ground
bit 26 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
AD[25]
AD[24]
21
22
I/O
I/O
bit 25 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
bit 24 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
SAF1562
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
V
I(VAUX3V3)
INTA#
3
4
-
O
GNDD
AD[26]
19
20
-
I/O
Product data sheet
Rev. 3 — 19 June 2012
5 of 121
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