NB6L14M
2.5 V/3.3 V 3.0 GHz
Differential 1:4 CML Fanout
Buffer
Multi-Level Inputs with Internal Termination
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Description
The NB6L14M is a 3.0 GHz differential 1:4 CML clock or data
fanout buffer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14M to accept various logic standards, such as
LVPECL, CML, or LVDS logic levels. The 16 mA differential CML
outputs provide matching internal 50
W
terminations and produce
400 mV output swings when externally terminated with a 50
W
resistor to V
CC
. The V
REFAC
reference output can be used to rebias
capacitor-coupled differential or single-ended input signals. The 1:4
fanout design was optimized for low output skew applications.
The NB6L14M is a member of the ECLinPS MAX™ family of high
performance clock and data products.
Features
MARKING
DIAGRAM*
16
1
QFN-16
MN SUFFIX
CASE 485G
NB6L
14M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
•
•
Input Clock Frequency > 3.0 GHz
Input Data Rate > 2.5 Gb/s
< 20 ps Within Device Output Skew
350 ps Typical Propagation Delay
90 ps Typical Rise and Fall Times
Differential CML Outputs, 340 mV Amplitude, Typical
CML Mode Operating Range: V
CC
= 2.375 V to 3.63 V with
GND = 0 V
Internal Input and Output Termination Resistors, 50
W
V
REFAC
Reference Output Voltage
-40°C to +85°C Ambient Operating Temperature
Available in 3 mm x 3 mm 16 Pin QFN
These are Pb-Free Devices
Q0
Q0
Q1
IN
VT
IN
Q2
Q2
Q1
EN
D
Q
Q3
VREFAC
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
1
April, 2008 - Rev. 3
Publication Order Number:
NB6L14M/D
NB6L14M
Q0
Q0
16
Q1
Q1
Q2
Q2
Q0
15
V
CC
GND
14
13
Q1
IN
VT 50
W
IN 50
W
/Q1
Exposed Pad (EP)
/Q0
1
2
3
4
5
Q3
6
Q3
7
V
CC
8
EN
12 IN
11 VT
10 V
REFAC
9
IN
D
Q
CLK
Q2
/Q2
EN
VREFAC
Q3
/Q3
Figure 2. QFN-16 Pinout
(Top View)
Table 1. EN TRUTH TABLE
IN
0
1
x
IN
1
0
x
EN
1
1
0
Q0:Q3
0
1
0+
Figure 3. Logic Diagram
Q0:Q3
1
0
1+
+ = On next negative transition of the input signal (IN).
x = Don't care.
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Name
Q1
Q1
Q2
Q2
Q3
Q3
V
CC
EN
I/O
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
-
LVTTL/LVCMOS
Description
Non-inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non-inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Non-inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Positive Supply Voltage
Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal D
FF
register is
clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
Inverted Differential Clock Input. Internal 50
W
Resistor to Termination Pin, VT.
Output Voltage Reference for capacitor-coupled inputs, only.
Internal 100
W
center-tapped Termination Pin for IN and IN.
LVPECL, CML,
LVDS
-
-
CML Output
CML Output
-
Non-inverted Differential Clock Input. Internal 50
W
Resistor to Termination Pin, VT.
Negative Supply Voltage
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to V
CC
.
The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
9
10
11
12
13
14
15
16
-
IN
V
REFAC
VT
IN
GND
V
CC
Q0
Q0
EP
LVPECL, CML,
LVDS
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to self-oscillation.
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NB6L14M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Mode
QFN-16
Oxygen Index: 28 to 34
Value
> 2 kV
> 200 V
Level 1
UL 94 V-0 @ 0.125 in
167
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
Io
I
IN
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input/Output
Input Current
Source or Sink Current (IN/IN)
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance
(Junction-to-Ambient) (Note 3)
Thermal Resistance (Junction-to-Case)
Wave Solder
Pb-Free
0 lfpm
500 lfpm
2S2P (Note 3)
QFN-16
QFN-16
QFN-16
"2.0
-40 to +85
-65 to +150
42
35
4
265
mA
°C
°C
°C/W
°C/W
°C/W
°C
Condition 1
GND = 0 V
GND = 0 V
-0.5 V
v
V
Io
v
V
CC
+ 0.5 V
Condition 2
Rating
4.0
4.5
"50
Unit
V
V
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6L14M
Table 5. DC CHARACTERISTICS, Multi-Level Inputs, CML Outputs
V
CC
= 2.375 V to 3.63 V, GND = 0 V, T
A
= -40°C to +85°C
Symbol
I
CC
Characteristic
Power Supply Current (Inputs and Outputs Open)
Min
80
Typ
100
Max
130
Unit
mA
CML OUTPUT
(Notes 4 and 5)
V
OH
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
OL
Output LOW Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED
(See Figures 5 and 6)
V
th
V
IH
V
IL
V
ISE
V
REFAC
V
REFAC
Output Reference Voltage (V
CC
w
2.5 V)
V
CC
- 1525
V
CC
- 1425
V
CC
- 1325
mV
Input Threshold Reference Voltage Range (Note 6)
Single-Ended Input High Voltage
Single-Ended Input LOW Voltage
Single-Ended Input Voltage Amplitude (V
IH
- V
IL
)
1100
V
th
+ 100
GND
200
V
CC
- 100
V
CC
V
th
- 100
V
CC
- GND
mV
mV
mV
mV
V
CC
- 40
3260
2460
V
CC
- 500
2800
2000
V
CC
- 10
3290
2490
V
CC
- 400
2900
2100
V
CC
3300
2500
V
CC
- 300
3000
2200
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(See Figures 7 and 8) (Note 7)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (IN-IN) (V
IHD-
V
ILD
)
Input Common Mode Range (Differential Configuration)
(Note 8)
Input HIGH Current IN/IN
(VT Open)
Input LOW Current IN/IN
(VT Open)
1200
GND
100
950
-150
-150
V
CC
V
IHD
- 100
V
CC
- GND
V
CC
– 50
+150
+150
mV
mV
mV
mV
mA
mA
LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS
V
IH
V
IL
I
IH
I
IL
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current, V
CC
= V
IN
= 3.63 V
Input LOW Current, V
CC
= 3.63 V, V
IN
= 0 V
2.0
GND
-150
-150
V
CC
0.8
+150
+150
V
V
mA
mA
TERMINATION RESISTORS
R
TIN
R
DIFF_IN
R
TOUT
Internal Input Termination Resistor (IN to VT)
Differential Input Resistance (IN to IN)
Internal Output Termination Resistor
40
80
40
50
100
50
60
120
60
W
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs loaded with 50
W
to V
CC
for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
is applied to the complementary input when operating in single-ended mode.
7. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
8. V
CMR
minimum varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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NB6L14M
Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.63 V, GND = 0 V, T
A
= -40°C to +85°C (Note 9)
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
) (Note 10)
f
in
≤
2.5 GHz
2.5 GHz
≤
f
in
≤
3.0 GHz
IN to Q
EN to IN, IN
EN to IN, IN
Min
180
100
Typ
340
250
2.5
230
300
300
5.0
f
in
≤
3.0 GHz
40
50
20
80
60
350
480
Gb/s
ps
ps
ps
ps
%
ps
0.2
20
100
90
V
CC
- GND
150
mV
ps
0.5
Max
Unit
mV
f
DATA
t
PD
t
S
t
H
t
SKEW
t
DC
t
JITTER
Maximum Operating Data Rate
Propagation Delay
Set-Up Time (Note 11)
Hold Time (Note 11)
Within-Device Skew (Note 12)
Device-to-Device Skew (Note 13)
Output Clock Duty Cycle
(Referenced Duty Cycle = 50%)
RMS Random Jitter (Note 14)
Peak-to-Peak Data Dependent Jitter
(Note 15)
f
IN
≤
3.0 GHz
f
DATA
≤
3.0 Gb/s
V
INPP
t
r
,t
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times
(20%-80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
INPP
(minimum) from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
CC
. Input edge rates
40 ps (20%-80%).
10. Input and output voltage swing is a single-ended measurement operating in differential mode.
11. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold times do not apply.
12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 23-1 and K28.5 at 2.5 Gb/s.
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