NB3N3011
3.3 V 100 MHz / 106.25 MHz
PureEdge Clock Generator
with LVPECL Differential
Output
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Description
The NB3N3011 is a Fibre Channel Clock Generator and uses a
26.5625 MHz crystal to synthesize 106.25 MHz or a 25 MHz crystal
to synthesize 100 MHz. The NB3N3011 has excellent <1 ps phase
jitter performance over the 637 kHz – 10 MHz integration range. The
NB3N3011 is packaged in an 8−Pin 4.4 mm x 3.0 mm TSSOP, making
it ideal for use in systems with limited board space.
Features
MARKING
DIAGRAM
311
YWW
AG
TSSOP−8
DT SUFFIX
CASE 948S
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
•
PureEdge Clock Family Provides Accuracy and Precision
•
One Differential LVPECL Output
•
Crystal Oscillator Interface Designed for Fundamental Mode 18 pF
•
•
•
•
•
•
•
Parallel Resonant Crystal (25 MHz or 26.5625 MHz)
Output Frequency: 106.25 MHz (26.5625 MHz Crystal) or 100 MHz
(25 MHz Crystal)
VCO Range: 760 MHz
−
950 MHz
RMS Phase Jitter @ 100 MHz, using a 25 MHz Crystal
(637 kHz
−
10 MHz): 0.29 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase noise:
Offset Noise Power
100 Hz
−108
dBc/Hz
1 kHz
−122
dBc/Hz
10 kHz
−135
dBc/Hz
100 kHz
−135
dBc/Hz
3.3 V Power Supply
−40°C
to 85°C Ambient Operating Temperature
These are Pb−Free Devices*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
X
IN
25 MHz
or
26.5625 MHz X
OUT
Crystal
Oscillator
Phase
Detector
Charge
Pump
VCO
850 MHz
w/26.5625
MHz Ref.
N =B8
LVPECL
Output
Q
100 MHz
or
Q 106.25 MHz
M =
B32
Figure 1. Logic Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2008
August, 2008
−
Rev. 1
1
Publication Order Number:
NB3N3011/D
NB3N3011
VCCA
VEE
XOUT
XIN
1
2
8
7
VCC
Q
Q
NC
NB3N3011
3
4
6
5
Figure 2. Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
Symbol
V
CCA
V
EE
X
OUT
X
IN
NC
Q
Q
V
CC
Type
Power
Power
Input
Input
Unused
Output
Output
Power
Description
Positive Analog Power Supply Pin. Connected to V
CC
with filter components (See Figure 8).
Negative Supply Pin.
Crystal Input (OUT).
Crystal Input (IN).
No Connect.
Inverted Differential Output. Typically terminated with 50
W
to V
CC
−2.0
V.
Noninverted Differential Output. Typically terminated with 50
W
to V
CC
−2.0
V.
Positive Digital Core Power Supply Pin. Connected to 3.3 V.
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 1)
Human Body Model
Machine Model
Pb−Free Pkg, TSSOP−8
Value
> 6 kV
> 200 V
Level 3
UL 94 V−0 @ 0.125 in
4150
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
O
q
JA
T
STG
Supply Voltage
Inputs
Output Current
Thermal Resistance (Junction−to−Ambient)
Storage Temperature
Continuous
Surge
0 Lfpm
500 Lfpm
Parameter
Value
4.6
−0.5
to V
CC
+ 0.5
50
100
142
103
−65
to 150
Unit
V
V
mA
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NB3N3011
Table 4. POWER SUPPLY DC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C
)
Symbol
V
CC
V
CCA
I
CCA
I
EE
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Included in I
EE
Conditions
Min
3.135
3.135
Typ
3.3
3.3
19
27
Max
3.465
3.465
23
31
Unit
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. LVPECL DC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C
)
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage (Note 2)
Output Low Voltage (Note 2)
Peak−to−Peak Output Voltage Swing
Conditions
Min
V
CC
−
1.4
V
CC
−
2.0
0.6
0.75
Typ
Max
V
CC
−
0.9
V
CC
−
1.7
1.0
Unit
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs terminated with 50
W
to V
CC
−
2.0 V. See Figures 4 and 12.
Table 6. PIN CHARACTERISTICS
Symbol
C
IN
Parameter
Input Capacitance
Conditions
Min
Typ
4
Max
Unit
pF
Table 7. CRYSTAL CHARACTERISTICS
(Fundamental Mode 18 pF Parallel Resonant Crystal
)
Parameter
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Conditions
Min
24
Typ
Max
30
50
7.0
Unit
MHz
W
pF
Table 8. AC CHARACTERISTICS,
(V
CC
= 3.3 V
±5%,
T
A
=
−40°C
to 85°C (Note 4))
Symbol
f
OUT
t
jit(∅)
Parameter
Output Frequency
RMS Phase Jitter (Random)
(Note 3)
Conditions
24 MHz
−
30 MHz Crystal
(Typ. 25 MHz
−
26.5625 MHz)
106.25 MHz; Integration Range:
637 kHz
−10
MHz
100 MHz; Integration Range:
637 kHz
−10
MHz
t
R
/t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80% (See Figure 7)
(See Figure 6)
275
48
Min
96
Typ
100/106.25
0.29
0.29
600
52
ps
%
Max
120
Unit
MHz
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Please refer to the Phase Noise Plot.
4. Output terminated with 50
W
to V
CC
−
2.0 V. See Figures 4 and 12.
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NB3N3011
NOISE POWER (dBc)
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
V
CC
LVPECL
Z = 50
W
V
EE
Q
50
W
−1.3
V
"
0.165 V
f
1
Offset Frequency
f
2
Q
SCOPE
50
W
Noise Power
Z = 50
W
Phase Noise Mask
RMS
+
Area Under the Masked Phase Noise Plot
Figure 4. Output Load AC Test Circuit
(Split Power Supply)
Figure 5. RMS Phase Jitter
Q
Q
Pulse Width
t
PERIOD
odc
+
tPW
Q
Clock
Outputs
Q
80%
20%
t
R
80%
V
SWING
20%
t
F
tPERIOD
Figure 6. Output Duty Cycle/Pulse Width/Period
Figure 7. Output Rise/Fall Time
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NB3N3011
APPLICATION INFORMATION
Power Supply Filtering
The NB3N3011 is a mixed analog/digital product, and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB3N3011 also
generates sub−nanosecond output edge rates, and therefore,
a good power supply bypassing scheme is a must.
The NB3N3011 provides separate power supplies for the
digital circuitry (V
CC
) and the internal PLL (V
CCA
). The
simplest form of noise isolation is a power supply filter on
the V
CCA
pin.
Figure 8 illustrates a typical power supply filter scheme.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
The purpose of this design technique is to try and isolate
the high switching noise of the digital outputs from the
relatively sensitive internal analog phase−locked loop. The
power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply
noise−related problems in most designs.
Crystal Oscillator Input Interface
Figure 9 illustrates a parallel resonant crystal with its
associated load capacitors. The capacitor values shown were
determined using a 26.5625 MHz, 18 pF parallel resonant
crystal and were chosen to minimize the ppm error.
Capacitor values can be adjusted slightly for different board
layouts to optimize accuracy.
3.3 V
V
CC
0.01
mF
10
W
V
CCA
0.01
mF
10
mF
Figure 8. Power Supply Filtering
C1
33 pF
X1
18 pF Parallel Crystal
C2
27 pF
X
OUT
The NB3N3011 features an integrated crystal oscillator to
minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
As the oscillator is somewhat sensitive to loading on its
inputs, the user is advised to mount the crystal as close to the
NB3N3011 as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
X
IN
Figure 9. Crystal Input Interface
APPLICATION SCHEMATIC
Figure 10 shows a schematic example of the NB3N3011.
An example of LVPECL termination is shown in this
schematic. Additional LVPECL termination approaches are
shown in the AND8020 Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
generating 106.25 MHz output frequency. The C1 = 27 pF
and C2 = 33 pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
V
CC
V
CC
R2
10
C3
10
mF
V
CCA
C4
0.01
mF
1
U1
V
CCA
2 V
EE
3 X
OUT
4
X
IN
V
CC
7
Q
6
Q
NC 5
Q
V
CC
= 3.3 V
C5
0.1
m
8
Q
V
CC
R3
133
Z
O
= 50
W
R5
133
+
Z
O
= 50
W
R4
82.5
−
R6
82.5
C2
33 pF
18 pF
X1
C1
27 pF
Figure 10. Typical Application Schematic
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