INTEGRATED CIRCUITS
HSTL16918
9-bit to 18-bit HSTL-to-LVTTL
memory address latch
Product data
2001 Jun 16
Philips
Semiconductors
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
FEATURES
•
Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet
Level III specifications
PIN CONFIGURATION
2Q1
1Q1
GND
D1
D2
V
CC
D3
1
2
3
4
5
6
7
8
9
48 V
CC
47 V
CC
46 1Q2
45 2Q2
44 GND
43 1Q3
42 2Q3
41 V
CC
40 1Q4
39 2Q4
38 GND
37 1Q5
36 2Q5
35 GND
34 1Q6
33 2Q6
32 V
CC
31 1Q7
30 2Q7
29 GND
28 1Q8
27 2Q8
26 V
CC
25 V
CC
•
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
•
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
•
Packaged in 48-pin plastic thin shrink small outline package
(TSSOP48)
DESCRIPTION
The HSTL16918 is a 9-bit to 18-bit D-type latch designed for
3.15 to 3.45 V V
CC
operation. The D inputs accept HSTL levels and
the Q outputs provide LVTTL levels.
The HSTL16918 is particularly suitable for driving an address bus to
two banks of memory. Each bank of nine outputs is controlled with
its own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two D-type latches
that provide true data (Q) at the outputs. While LE is LOW the Q
outputs of the corresponding nine latches follow the D inputs. When
LE is taken HIGH, the Q outputs are latched at the levels set up at
the D inputs.
The HSTL16918 is characterized for operation from 0 to +70
°C.
D4
GND
1LE 10
GND 11
V
REF
12
GND 13
2LE 14
GND 15
D5 16
D6 17
D7 18
V
CC
19
D8 20
D9 21
GND 22
2Q9 23
1Q9 24
SW00768
ORDERING INFORMATION
PACKAGES
48-pin plastic thin shrink small outline package
(TSSOP48)
TEMPERATURE RANGE
0 to +70
°C
ORDER CODE
HSTL16918DGG
DWG NUMBER
SOT362-1
2001 Jun 16
2
853-2258 26484
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
PIN DESCRIPTION
PIN
4, 5, 7, 8, 16, 17,
18, 20, 21
2, 46, 43, 40, 37,
34, 31, 28, 24
1, 45, 42, 39, 36,
33, 30, 27, 23
10
14
12
6, 19, 25, 26, 32,
41, 47, 48
3, 9, 11, 13, 15,
22, 29, 35, 38, 44
SYMBOL
D[1–9]
1Q[1–9]
Outputs
2Q[1–9]
Inputs
FUNCTION
LOGIC DIAGRAM (positive logic)
V
REF
12
1LE
D1
10
4
1D
2
C1
1Q1
1LE
2LE
V
REF
V
CC
GND
Latch enable
Reference voltage
Supply voltage
Ground
2LE
14
1D
1
C1
2Q1
TO EIGHT OTHER CHANNELS
SW00769
FUNCTION TABLE
INPUTS
LE
L
L
H
D
H
L
X
OUTPUT
Q
H
L
Q
0 1
NOTE:
1. Output level before the indicated steady-state input conditions
were established.
2001 Jun 16
3
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
ABSOLUTE MAXIMUM RATINGS
1
Over operating free-air temperature range (unless otherwise noted).
SYMBOL
V
CC
V
I
V
O
I
IK
I
OK
I
O
θ
JA
T
stg
PARAMETER
Supply voltage range
Input voltage range
2
Output voltage range
2
Input clamp current
Output clamp current
3
Continuous output current
Continuous current through each V
CC
or GND
Package thermal impedance
4
Storage temperature range
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–50
±50
±50
±100
89
–65 to +150
UNIT
V
V
V
mA
mA
mA
mA
°C/W
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This current flows only when the output is in the high state and V
O
> V
CC
.
4. The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
1
LIMITS
SYMBOL
V
CC
V
REF
V
I
V
IH
V
IL
V
IH
V
IL
I
OH
I
OL
T
amb
Supply voltage
Reference voltage
Input voltage
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature range
0
All inputs
All inputs
All inputs
All inputs
V
REF
+ 100 mV
V
REF
– 100 mV
–24
24
+70
PARAMETER
Min
3.15
0.68
0
V
REF
+ 200 mV
V
REF
– 200 mV
0.75
Nom
Max
3.45
0.9
1.5
UNIT
V
V
V
V
V
V
V
mA
mA
°C
NOTE:
1. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation.
2001 Jun 16
4
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted).
LIMITS
SYMBOL
V
IK
V
OH
V
OL
Control inputs
I
I
Data inputs
V
REF
I
CC
Control inputs
C
I
C
O
Data inputs
Outputs
PARAMETER
TEST CONDITIONS
V
CC
= 3.15 V; I
I
= –18 mA
V
CC
= 3.15 V; I
OH
= –24 mA
V
CC
= 3.15 V; I
OL
= 24 mA
V
CC
= 3.45 V; V
I
= 0 or 1.5 V
V
CC
= 3.45 V; V
I
= 0 or 1.5 V
V
CC
= 3.45 V; V
REF
= 0.68 V or 0.9 V
V
CC
= 3.45 V; V
I
= 0 or 1.5 V
V
CC
= 0 or 3.3 V; V
I
= 0 or 3.3 V
V
CC
= 0 or 3.3 V; V
I
= 0 or 3.3 V
V
CC
= 0 V; V
O
= 0 V
50
2
2.5
4
2.4
0.5
±5
±5
90
100
Min
Typ
1
Max
–1.2
UNIT
V
V
V
µA
µA
µA
mA
pF
pF
pF
NOTE:
1. All typical values are at V
CC
= 3.3 V; T
amb
= 25
°C.
TIMING REQUIREMENTS
Over recommended operating free-air temperature range (unless otherwise noted).
SYMBOL
t
w
t
su
t
h
t
ldr
PARAMETER
Pulse duration
Setup time
Hold time
Data race condition time
1
TEST CONDITIONS
LE LOW (Figure 1)
D before LE
↑
(Figure 2)
D after LE
↑
(Figure 2)
D after LE
↓
V
CC
= 3.3 V
±0.15
V
Min
3
2
1
0
Max
UNIT
ns
ns
ns
ns
NOTE:
1. This is the maximum time after LE switches LOW that the data input can return to the latched state from the opposite state without producing
a glitch on the output.
SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; V
REF
= 0.75 V.
SYMBOL
PARAMETER
FROM
(INPUT)
D
t
pd
Propagation delay (Figure 3)
LE
Q
1.9
4.2
ns
TO
(OUTPUT)
Q
V
CC
= 3.3 V
±0.15
V
Min
1.9
Max
3.4
ns
UNIT
SIMULTANEOUS SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; V
REF
= 0.75 V
SYMBOL
PARAMETER
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
Q
V
CC
= 3.3 V
±0.15
V
Min
1.9
1.9
Max
4.4
5.2
ns
ns
UNIT
t
pd
Propagation delay; all outputs switching
g
y
g
(Figure 3)
2001 Jun 16
5
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