3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
16,384
X
16,384
IDT72V71660
FEATURES:
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DESCRIPTION:
The IDT72V71660 has a non-blocking switch capacity of 2,048 x 2,048
channels at 2.048Mb/s, 4,096 x 4,096 channels at 4.096Mb/s, and 8,192 x
8,192 channels at 8.192Mb/s and 16,384 x 16,384 channels at 16.384Mb/s.
With 64 inputs and 64 outputs, programmable per stream control, and a variety
of operating modes the IDT72V71660 is designed for the TDM time slot
interchange function in either voice or data applications.
Some of the main features of the IDT72V71660 are LOW power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, output enable and processor mode.
The IDT72V71660 is capable of switching up to 16,384 x 16,384 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.
•
16K x 16K non-blocking switching at 16.384Mb/s
64 serial input and output streams
Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or
16.384Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Automatic identification of ST-BUS
®
and GCI bus interfaces
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high-impedance output control
Direct microprocessor access to all internal memories
Memory block programming for quick setup
IEEE-1149.1 (JTAG) Test Port
3.3V Power Supply
Available in 208-pin (17mm x 17mm) Plastic Ball Grid Array
(PBGA) and 208-pin (28mm x 28mm) Plastic Quad Flatpack
(PQFP) packages
°
°
Operating Temperature Range -40°C to +85°C
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
RESET
ODE
TX0
RX0
RX1
Data Memory
MUX
TX1
Receive
Serial Data
Streams
Internal
Registers
RX63
Connection
Memory
Transmit
Serial Data
Streams
TX3
1
TX32/OEI0
TX33/OEI1
TX63/OEI31
Timing Unit
Microprocessor Interface
JTAG Port
CLK
FP FE/HCLK WFPS
DS
CS
R/W
A0-A15
DTA
D0-D15
TMS TDI TCK TDO
TRST
5905 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
JUNE 2004
DSC-5905/10
1
2004
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
NAME
A0-15
Address 0 to 15
CLK
CS
D0-15
DS
DTA
Clock
Chip Select
Data Bus 0-15
Data Strobe
Data Transfer
Acknowledgment
I/O DESCRIPTION
I These address lines access all internal memories.
I
I
Serial clock for shifting data in/out on the serial data streams. Depending upon the value programmed, this
input accepts a 4.096, 8.192 or 16.384 MHz clock. See the Control Register bits on Table 5 for the values.
This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V71660.
I/O These pins are the data bits of the microprocessor port.
I This active LOW input works in conjunction with
CS
to enable the read and write operations and enables the
data bus lines (D0-D15).
O
Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes
high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is in high-impedance.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the
HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse mode (WFPS).
(1)
FE/HCLK Frame Evaluation/
HCLK Clock
I
FP
Frame Pulse
I
GND
ODE
Ground
Output Drive Enable
I
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals
formatted according to ST-BUS
®
and GCI specifications. When pin WFPS is HIGH, this pin accepts a
negative frame pulse, which conforms to the WFPS format.
Ground Rail.
This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand
By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per-channel control bit in the Connection Memory.
This input puts the IDT72V71660 into a reset state that clears the device internal counters, registers and
brings TX0-63 and D0-D15 into a high-impedance state. The
RESET
pin must be held LOW for a
minimum of 20ns to properly reset the device.
This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.
Serial data input stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or
16.384Mb/s, depending upon the value programmed in the Control Register.
Provides the clock to the JTAG test logic.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
JTAG signal that controls the state transitions of the Test Access Port controller. This pin is pulled HIGH by an
internal pull-up when not driven.
Asynchronously initializes the JTAG Test Access Port controller by putting it in the Test-Logic-Reset state. This
pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V71660 is in the normal functional mode.
Serial data output stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,
or 16.384Mb/s, depending upon the value programmed in the Control Register.
When all 64 output streams are selected via Control Register, these pins are the output streams TX32 to TX63
and may operate at a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s. When output enable
function is selected, these pins reflect the active or high-impedance status for the
corresponding output stream OEI0-31.
+3.3 Volt Power Supply.
When 1, enables the wide frame pulse (WFPS) Frame Alignment interface. When 0, the device operates in
ST-BUS
®
/GCI mode.
(2)
RESET
Device Reset
I
R/W
RX0-63
TCK
TDI
TDO
TMS
TRST
Read/Write
Data Stream
Input 0 to 63
Test Clock
Test Serial Data In
Test Serial Data Out
Test Mode Select
Test Reset
I
I
I
I
O
I
I
TX0-31
TX Output 0 to 31
(Three-state Outputs)
O
O
TX32-63/ TX Output 32 to 63/
OEI0-31 Output Enable
Indication 0 to 31
(Three-state Outputs)
V
CC
V
CC
WFPS
Wide Frame Pulse Select
I
NOTES:
1. For compatibility with the IDT72V73273/63 device, this pin should be logic High.
2. For compatibility with the IDT72V73273/63 device, this pin should be logic Low.
4
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
The 64 serial input streams (RX) of the IDT72V71660 can run up to
16.384Mb/s allowing 256 channels per 125µs frame. The data rates on the
output streams (TX) are identical to those on the input streams (RX).
With two main operating modes, Processor Mode and Connection Mode, the
IDT72V71660 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V71660
has a Frame Evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V71660 also provides a JTAG Test Access Port, memory block
programming, a simple microprocessor interface and automatic ST-BUS
®
/GCI
sensing to shorten setup time, aid in debugging and ease use of the device
without sacrificing capabilities.
setup the device. The IDT72V71660 provides two different interface timing
modes, ST-BUS
®
or GCI. The IDT72V71660 automatically detects the pres-
ence of an input frame pulse and identifies it as either ST-BUS
®
or GCI.
In ST-BUS
®
, when running at 16.384 MHz, data is clocked out on the falling
edge and is clocked in on the subsequent rising-edge. At all other data rates,
there are two clock cycles per bit and every second falling edge of the master
clock marks a bit boundary and the data is clocked in on the rising edge of CLK,
three quarters of the way into the bit cell. See Figure 14 for timing.
In GCI format, when running at 16.384 MHz, data is clocked out on the rising
edge and is clocked in on the subsequent falling edge. At all other data rates,
there are two clock cycles per bit and every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell. See Figure 15 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment . Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5
master clock (CLK) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71660 provides the Frame Evaluation input to determine
different data input delays with respect to the frame pulse FP. A measurement
cycle is started by setting the Start Frame Evaluation bit of the Control Register
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
Register is changed from LOW to HIGH, the evaluation starts. Two frames later,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 11 of the Frame Alignment Register. The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (Frame
Evaluation) is evaluated against the falling edge of the ST-BUS
®
frame pulse.
In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.
MEMORY BLOCK PROGRAMMING
The IDT72V71660 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.
The block programming mode is enabled by setting the Memory Block
Program bit of the Control Register HIGH. When the Block Programming Enable
bit of the Control Register is set to HIGH, the Block Programming Data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory
block programming is complete, the device resets the Block Programming
Enable , BPD 1-0 and MBP bits to zero.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (FP) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
half (8 least significant bits) of the Connection Memory is output every frame until
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.
The two most significant bits of the Connection Memory are used to control
the per-channel mode of the out put streams. Specifically, the MOD1-0 bits are
used to select Processor Mode, Constant or Variable delay Mode, and the high-
impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel. In other words, the ODE pin and Output Stand By control bit are master
output enables for the device (See Table 3).
SERIAL DATA INTERFACE TIMING
When a 16.384Mb/s serial data rate is required, the master clock frequency
will be running at 16.384 MHz resulting in a single-bit per clock. For all other
cases, 2.048Mb/s, 4.096Mb/s, and 8.192Mb/s, the master clock frequency will
be twice the data rate on the serial streams, resulting in two clocks per bit. Use
Table 5 to determine clock speed and the DR1-0 bits in the Control Register to
5
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