82541ER Gigabit Ethernet Controller
Networking Silicon
Datasheet
Product Features
■
■
■
PCI Bus
— PCI revision 2.3, 32-bit, 33/66 MHz
— Algorithms that optimally use advanced PCI,
MWI, MRM, and MRL commands
— 3.3 V (5 V tolerant PCI signaling)
MAC Specific
— Low-latency transmit and receive queues
— IEEE 802.3x-compliant flow-control support
with software-controllable thresholds
— Caches up to 64 packet descriptors in a single
burst
— Programmable host memory receive buffers
(256 B to 16 KB) and cache line size (16 B to
256 B)
— Wide, optimized internal data path
architecture
— 64 KB configurable Transmit and Receive
FIFO buffers
PHY Specific
— Integrated for 10/100/1000 Mb/s operation
— IEEE 802.3ab Auto-Negotiation support
— IEEE 802.3ab PHY compliance and
compatibility
— State-of-the-art DSP architecture implements
digital adaptive equalization, echo
cancellation, and cross-talk cancellation
■
■
■
■
— Automatic polarity detection
— Automatic detection of cable lengths and
MDI vs. MDI-X cable at all speeds
Host Off-Loading
— Transmit and receive IP, TCP, and UDP
checksum off-loading capabilities
— Transmit TCP segmentation
— Advanced packed filtering
— Jumbo frame support up to 16 KB
— Intelligent Interrupt generation (multiple
packets per interrupt)
Manageabiltiy
— Network Device Class Power Management
Specification 1.1
— Compliance with PCI Power Management
1.1 and ACPI 2.0
— SNMP and RMON statistic counters
— D0 and D3 power states
Additional Device
— Four programmable LED outputs
— On-chip power control circuitry
— BIOS LAN Disable pin
— JTAG (IEEE 1149.1) Test Access Port built
in silicon
Lead-free
a
196-pin Ball Grid Array (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUxxxxxx.
a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at
<1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other
Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of
the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen-
tative
Revision 4.1
September 2006
Revision History
Date
Aug 2003
Mar 2004
Oct 2004
Revision
2.0
3.0
3.1
Non-classified release.
Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the
C-0 stepping.
•
•
Corrected EEMODE signal description.
Updated signal names to match design guide and reference schematics.
• Added lead free information.
• Added information about migrating from a 2-layer 0.36 mm wide-trace
substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section
on Package and Pinout Information.
Nov 2004
3.2
• Added statement that no changes to existing soldering processes are
needed for the 2-layer 0.32 mm wide-trace substrate change in the
section describing “Package Information”.
•
Corrected pinout discrepancies between sections “Signal Descriptions”
and “Package and Pinout Information”.
• Added new maximum values for DC supply voltages on 1.2 V and 1.8 V
pins. See Table 2, Recommended Operating Conditions and Table 6, DC
Characteristics.
• Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14,
and H14.
• Removed all references to CLK_RUN# signal.
Apr 2005
July 2005
Aug 2005
June 2006
June 2006
Aug 2006
Sept 2006
3.5
3.6
3.7
3.8
3.9
4.0
4.1
• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash
functionality is not used then an external pull-down resistor is required.
• Added pin C8 description to Table 29 and Table 31.
• Corrected 25 MHz Clock Input Requirements in Table 13.
• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash
functionality is not used then an external pull-up resistor is required.
• Updated Table 13 “25 MHz Clock Input Requirements”.
• Updated Table 40 descriptions for pins A10, B10, and C9.
• Updated pinout descriptions from Tables 25 - 42 to match Figure 13.
• Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved
the note following Table 5 before Table 3 “3.3V Supply Voltage Ramp”.
Notes
Jan 2005
3.3
Feb 2005
3.4
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82541ER Gigabit Ethernet Controller may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2006
*Third-party brands and names are the property of their respective owners.
ii
Datasheet
82541ER Gigabit Ethernet Controller
Contents
1.0
Introduction ...................................................................................................................... 1
1.1
1.2
1.3
1.4
2.0
3.0
Document Scope................................................................................................... 1
Reference Documents...........................................................................................2
Product Codes....................................................................................................... 2
Block Diagram ....................................................................................................... 3
Product Code.................................................................................................................... 5
Signal Descriptions.......................................................................................................... 7
3.1
3.2
Signal Type Definitions.......................................................................................... 7
PCI Bus Interface Signals (56) ..............................................................................7
3.2.1 PCI Address, Data and Control Signals (44) ............................................ 8
3.2.2 Arbitration Signals (2)............................................................................... 9
3.2.3 Interrupt Signal (1)....................................................................................9
3.2.4 System Signals (3) ................................................................................... 9
3.2.5 Error Reporting Signals (2).....................................................................10
3.2.6 Power Management Signals (2) .............................................................10
EEPROM and Serial FLASH Interface Signals (9)..............................................10
Miscellaneous Signals.........................................................................................11
3.4.1 LED Signals (4) ......................................................................................11
3.4.2 Other Signals (4) ....................................................................................11
PHY Signals ........................................................................................................11
3.5.1 Crystal Signals (2) ..................................................................................11
3.5.2 Analog Signals (10) ................................................................................12
Test Interface Signals (6) ....................................................................................12
Power Supply Connections .................................................................................13
3.7.1 Digital and Analog Supplies ...................................................................13
3.7.2 Grounds, Reserved Pins and No Connects ...........................................13
3.7.3 Voltage Regulation Control Signals (2) ..................................................13
Absolute Maximum Ratings.................................................................................15
Targeted Recommended Operating Conditions..................................................15
4.2.1 General Operating Conditions................................................................15
4.2.2 Voltage Ramp and Sequencing Recommendations...............................16
DC Specifications ................................................................................................18
AC Characteristics...............................................................................................21
Timing Specifications ..........................................................................................23
4.5.1 PCI Bus Interface ...................................................................................23
4.5.1.1 PCI Bus Interface Clock ............................................................23
4.5.1.2 PCI/PCI-X Bus Interface Timing ................................................24
4.5.2 Link Interface Timing ..............................................................................27
4.5.3 EEPROM Interface.................................................................................27
Package Information ...........................................................................................29
Thermal Specifications ........................................................................................31
3.3
3.4
3.5
3.6
3.7
4.0
Voltage, Temperature, and Timing Specifications ......................................................15
4.1
4.2
4.3
4.4
4.5
5.0
Package and Pinout Information ..................................................................................29
5.1
5.2
Datasheet
iii
82541ER Gigabit Ethernet Controller
5.3
5.4
Pinout Information ............................................................................................... 32
Visual Pin Assignments....................................................................................... 42
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
82541ER Block Diagram....................................................................................... 3
AC Test Loads for General Output Pins.............................................................. 23
PCI Clock Timing ................................................................................................ 23
PCI Bus Interface Output Timing Measurement ................................................. 24
PCI Bus Interface Input Timing Measurement Conditions .................................. 25
TVAL (max) Rising Edge Test Load.................................................................... 25
TVAL (max) Falling Edge Test Load ................................................................... 26
TVAL (min) Test Load ......................................................................................... 26
TVAL Test Load (PCI 5 V Signaling Environment) ............................................. 26
Link Interface Rise/Fall Timing............................................................................ 27
82541ER Mechanical Specifications................................................................... 29
196 PBGA Package Pad Detail........................................................................... 30
Visual Pin Assignments....................................................................................... 42
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Absolute Maximum Ratings ................................................................................ 15
Recommended Operating Conditions ................................................................ 15
3.3V Supply Voltage Ramp ................................................................................. 16
1.8V Supply Voltage Ramp ................................................................................. 16
1.2V Supply Voltage Ramp ................................................................................. 17
DC Characteristics .............................................................................................. 18
Power Specifications - D0a ................................................................................. 18
Power Specifications - D3cold ............................................................................ 18
Power Specifications D(r) Uninitialized) .............................................................. 19
Power Specifications - Complete Subsystem ..................................................... 19
I/O Characteristics............................................................................................... 20
AC Characteristics: 3.3 V Interfacing .................................................................. 21
25 MHz Clock Input Requirements ..................................................................... 21
Reference Crystal Specification Requirements................................................... 22
Link Interface Clock Requirements ..................................................................... 22
EEPROM Interface Clock Requirements ............................................................ 22
AC Test Loads for General Output Pins.............................................................. 22
PCI Bus Interface Clock Parameters .................................................................. 23
PCI Bus Interface Timing Parameters................................................................. 24
PCI Bus Interface Timing Measurement Conditions ........................................... 25
Rise and Fall Times ............................................................................................ 27
Link Interface Clock Requirements ..................................................................... 27
Link Interface Clock Requirements ..................................................................... 27
Thermal Characteristics ...................................................................................... 31
PCI Address, Data and Control Signals .............................................................. 32
PCI Arbitration Signals ........................................................................................ 32
Interrupt Signals .................................................................................................. 32
System Signals ................................................................................................... 32
Error Reporting Signals....................................................................................... 33
Power Management Signals ............................................................................... 33
Serial EEPROM Interface Signals....................................................................... 33
iv
Datasheet
82541ER Gigabit Ethernet Controller
32
33
34
35
36
37
38
39
40
41
42
Serial FLASH Interface Signals...........................................................................33
LED Signals.........................................................................................................33
Other Signals.......................................................................................................33
IEEE Test Signals ...............................................................................................34
PHY Signals ........................................................................................................34
Test Interface Signals..........................................................................................34
Digital Power Signals ..........................................................................................34
Analog Power Signals .........................................................................................35
Grounds and No Connect Signals.......................................................................35
Voltage Regulation Control Signals.....................................................................35
Signal Names in Pin Order..................................................................................36
Datasheet
v
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
