LVDS Frequency-Programmable VCXO
IDT8N4SV75
DATA SHEET
General Description
The IDT8N4SV75 is a LVDS Frequency-Programmable VCXO with
very flexible frequency and pull-range programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm
x 1.55mm package.
The device can be factory-programmed to any frequency in the
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
to the very high degree of frequency precision of 218Hz or better.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
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Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Frequency programming resolution is 218Hz and better
Factory-programmable VCXO pull range and control voltage
polarity
Absolute pull-range (APR) programmable from ±4.5 to
±754.5ppm
One 2.5V / 3.3V LVDS clock output
Output enable control input, LVCMOS/LVTTL compatible
RMS phase jitter @ 156.25MHz (12kHz - 20MHz):
0.53ps (typical)
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
Block Diagram
Pin Assignment
VC 1
6 V
DD
5 nQ
4 Q
OSC
114.285 MHz
2
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
OE 2
GND 3
÷MINT,
MFRAC
7
VC
A/D
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
7
IDT8N4SV75
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
OE
Pullup
IDT8N4SV75CCD
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©2013 Integrated Device Technology, Inc.
IDT8N4SV75 Data Sheet
LVDS FREQUENCY PROGRAMMABLE VCXO
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4, 5
6
Name
VC
OE
GND
Q, nQ
V
DD
Input
Input
Power
Output
Power
Pullup
Type
Description
VCXO Control Voltage input.
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Differential clock output pair. LVDS interface levels.
Power supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
OE
VC
Test Conditions
Minimum
Typical
5.5
10
50
Maximum
Units
pF
pF
k
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
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©2013 Integrated Device Technology, Inc.
IDT8N4SV75 Data Sheet
LVDS FREQUENCY PROGRAMMABLE VCXO
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
Principles of Operation
The block diagram consists of the internal 3
RD
overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock® NG VCO along with the
Pre-divider (P), the feedback divider (M) and the post divider (N). The
P, M,
and
N
dividers determine the output frequency based on the
f
XTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
to two different factory pre-set configuration settings. The
configuration is selected via the FSEL pin. Changing the FSEL
control results in an immediate change of the output frequency to the
selected register values. The
P, M,
and
N
frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency f
OUT
is calculated by:
1
MFRAC
+ 0.5
-
f OUT
=
f XTAL
------------
MINT
+
------------------------------------
P
N
18
2
Table 3C. Frequency Selection
Input
FSEL
0 (default)
1
Selects
Frequency 0
Frequency 1
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document. For more
information on programming capabilities of the device for custom
frequency and pull range configurations, see the
FemtoClock NG
Ceramic 5x7 Module Programming Guide.
(1)
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
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©2013 Integrated Device Technology, Inc.
IDT8N4SV75 Data Sheet
LVDS FREQUENCY PROGRAMMABLE VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability
.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
DD
+ 0.5V
10mA
15mA
49.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
=
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
140
Maximum
3.465
175
Units
V
mA
Table 4B. Power Supply DC Characteristics, V
DD
=
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
136
Maximum
2.625
170
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristic, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
OE
OE
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
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©2013 Integrated Device Technology, Inc.
IDT8N4SV75 Data Sheet
LVDS FREQUENCY PROGRAMMABLE VCXO
Table 4D. LVDS DC Characteristics, V
DD
=
3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.14
1.23
Test Conditions
Minimum
247
Typical
330
Maximum
454
50
1.31
50
Units
mV
mV
V
mV
Table 4E. LVDS DC Characteristics, V
DD
=
2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.13
1.22
Test Conditions
Minimum
247
Typical
320
Maximum
454
50
1.30
50
Units
mV
mV
V
mV
IDT8N4SV75CCD
REVISION B NOVEMBER 6, 2013
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©2013 Integrated Device Technology, Inc.
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