MK2308-2
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Description
The MK2308-2 is a low jitter, low skew, high
performance Phase-Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3 V. The MK2308-2 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the MK2308-2 has the lowest jitter.
Features
•
•
•
•
•
•
•
Packaged in 16-pin SOIC
Zero input-output delay
Four 1X outputs plus four 1/2X outputs
Output to output skew is less than 250 ps
Output clocks up to 160 MHz at 3.3 V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
spectrum clock generators
•
Spread Smart
TM
technology works with spread
•
Advanced, low power, sub micron CMOS process
•
Operating voltage of 3.3 V or 5 V
Block Diagram
VDD
2
CLKA1
FBIN
CLKIN
CLKA2
CLKA3
CLKA4
BANK
A
PLL
/2
CLKB1
CLKB2
S2, S1
2
Control
Logic
CLKB3
CLKB4
BANK
B
2
GND
MDS 2308-2 B
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 111103
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
MK2308-2
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Feedback Configuration Table
Feedback From
Bank A
Bank B
CLKA1:A4
CLKIN
2XCLKIN
CLKB1:B4
CLKIN/2
CLKIN
16-pin (150 mil) SOIC
Output Clock Mode Select Table
S2
0
0
1
1
S1
0
1
0
1
Clocks A1:A4
Tri-state (high impedance)
Running
Running
Running
Clocks B1:B4
Tri-state (high impedance)
Tri-state (high impedance)
Running
Running
Internet Generation
None
PLL
Buffer only (no zero delay)
PLL
PLL Status
On
On
Off
On
Pin Descriptions
Pin
Number
1
2-3
4
5
6-7
8
9
10 - 11
12
13
14 - 15
16
Pin
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
CLKB1:B4
GND
VDD
CLKA1:A4
FBIN
Pin
Type
Input
Output
Power
Power
Output
Input
Input
Output
Power
Power
Output
Input
Pin Description
Clock input. Connect to input clock source.
Clock A bank of four outputs.
Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).
Connect to ground.
Clock B bank of four outputs. These are low skew divide by two of bank A.
Select input 2. Selects mode for outputs per table above.
Select input 1. Selects mode for outputs per table above.
Clock B bank of four outputs. These are low skew divide by two of bank A.
Connect to ground.
Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).
Clock A bank of four outputs.
Feedback input. Determines outputs per table above.
MDS 2308-2 B
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111103
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-2
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
External Components
The MK2308-2 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33Ω
series terminating resistor should be used on each clock output to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2308-2. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°C
-65 to +150
°C
175
°C
260
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+5.5
Units
°C
V
DC Electrical Characteristics
VDD=3.3 V ±10%,
Temp 0 to +70°
/-40
to +85° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
Conditions
CLKIN pin only
CLKIN pin only
Min.
3.0
(VDD/2)+1
2
Typ.
VDD/2
VDD/2
Max.
5.5
(VDD/2)-1
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -18 mA
I
OL
= 18 mA
I
OH
= -5 mA
2.4
0.4
VDD-0.4
MDS 2308-2 B
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111103
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-2
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Parameter
Operating Supply Current
100 MHz, CLKIN
Short Circuit Current
Input Capacitance
Symbol
IDD
I
OS
C
IN
Conditions
No Load
S1=S2=1
Each output
S1, S1, FBIN
Min.
Typ.
44
± 65
7
Max.
Units
mA
mA
pF
AC Electrical Characteristics
VDD = 3.3V ±10%,
Temp 0 to +70°/ -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Device to Device skew, equally
loaded
Output to Output skew, equally
loaded
Maximum Absolute Jitter
Cycle to Cycle Jitter
Symbol
Conditions
FBIN to CLKA1
S1=S2=1
FBIN to CLKA1
S1=S2=1
Min.
20
20
Typ.
Max. Units
160
160
1.5
1.5
MHz
MHz
ns
ns
%
ps
ps
ps
400
400
400
±250
1
ps
ps
ps
ps
ms
t
OR
t
OF
0.8 to 2.0 V, C
L
=30 pF
0.8 to 2.0 V, C
L
=30 pF
at 1.4V
rising edges at VDD/2
rising edges at VDD/2
300
30 pF loads
66.67 MHz outputs
15 pF loads
66.67 MHz outputs
40
50
60
700
200
Skew from Output Bank A to
Output Bank B
Delay CLKIN Rising Edge to
FBIN Rising Edge
PLL Lock Time
t
LOCK
All outputs equally
loaded
measured at VDD/2
Stable power supply,
valid clocks on CLKIN,
FBIN
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 2308-2 B
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111103
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-2
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Package Outline and Package Dimensions
(16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Symbol
Min
Max
Inches
Min
Max
16
E
INDEX
AREA
H
1 2
D
A
A1
B
C
D
E
e
H
h
L
α
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0
°
8
°
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.3859
.3937
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0
°
8
°
A
A1
h x 45
C
-C-
e
B
SEATING
PLANE
L
.10 (.004)
C
Ordering Information
Part / Order Number
MK2308S-2
MK2308S-2T
MK2308S-2I
MK2308S-2IT
Marking
MK2308S-2
MK2308S-2T
MK2308S-2I
MK2308S-2IT
Shipping
packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
Temperature
0 to 70° C
0 to 70° C
-40 to +85° C
-40 to +85° C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2308-2 B
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111103
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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