Low Cost, Balanced
Line Receiver ICs
THAT
1250, 1253, 1256
FEATURES
• Good CMRR: typ. 50 dB at 60Hz
• Low cost, self-contained
• Excellent audio performance
– Wide bandwidth: typ. >8.6 MHz
– High slew rate: typ. 12 V/μs
– Low distortion: typ. 0.0006% THD
– Low noise: typ. -103 dBu
• Low current: typ. 2 mA
• Several gains: 0 dB, ±3 dB, ±6 dB
• Industry Standard Pinout
• Current Shunt Monitors
• Instrumentation Amplifiers
• Differential Amplifiers
• Precision Summers
APPLICATIONS
• Balanced Audio Line Receivers
Description
The THAT 1250-series of precision differential
amplifiers was designed primarily for use as balanced
line receivers for audio applications. Gains of 0 db, ±3
dB, and ±6 dB are available to suit various applications
requirements.
These devices include on-board precision thin-
film resistors which offer good matching and excellent
tracking due to their monolithic construction.
Manufactured in THAT Corporation’s proprietary
complementary dielectric isolation (DI) process, the
THAT 1250-series provides the sonic benefits of
discrete designs with the simplicity, reliability, matching
and small size of an integrated solution.
All three versions of the part typically exhibit 50
dB of common-mode rejection. With 12 V/μs slew rate,
>8.6 MHz bandwidth, and 0.0006% THD, these
devices are sonically transparent. Moreover, current
consumption is typically a low 2 mA. Both surface-
mount and DIP packages are available.
The THAT 1256 is pin-compatible with the TI
INA137 and Analog Devices SSM2143, while the THAT
1250 is pin-compatible with the TI INA134 and Analog
Devices SSM2141.
Vcc
Pin Name
Ref
DIP Pin
1
2
3
4
5
6
7
8
SO Pin
1
2
3
4
5
6
7
8
In-
R
1
R
2
Sense
In-
In+
Vee
Vout
R
3
In+
R
4
Ref
Sense
Vout
Vcc
NC
Table 1. 1250-series pin assignments
Vee
Part no.
THAT1250
THAT1253
THAT1256
Gain
0 dB
-3 dB
-6 dB
NC
R
1
, R
3
R
2
, R
4
Gain
0 dB
±3 dB
±6 dB
Plastic DIP
1250P08-U
1253P08-U
1256P08-U
Plastic SO
1250S08-U
1253S08-U
1256S08-U
Figure 1. THAT 1250-series equivalent circuit diagram
Table 2. Ordering information
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2008, THAT Corporation
Document 600068 Rev 02
Document 600068 Rev 02
Page 2 of 8
THAT 1250 Series
Low-cost Balanced Line Receiver ICs
SPECIFICATIONS
1
Absolute Maximum Ratings
2,3
Supply Voltages (V
CC
- V
EE
)
Maximum In
-
or In
+
Voltage
Max/Min Ref or Sense Voltage
Maximum Output Voltage (V
OM
)
40V
-50V + V
CC
, 50V + V
EE
V
CC
+ 0.5V, V
EE
- 0.5V
V
CC
+ 0.5V, V
EE
- 0.5V
Storage Temperature Range (T
ST
)
Operating Temperature Range (T
OP
)
Output Short-Circuit Duration (t
SH
)
Junction Temperature (T
J
)
-40 to +125 ºC
0 to +85 ºC
Continuous
+125 ºC
Electrical Characteristics
2,4
Parameter
Supply Current
Supply Voltage
Input Voltage Range
Symbol
I
CC
V
CC
-V
EE
V
IN-DIFF
Differential (equal and opposite swing)
1250 (0dB gain)
1253 (-3dB gain)
1256 (-6dB gain)
Common Mode
1250 (0dB gain)
1253 (-3dB gain)
1256 (-6dB gain)
Differential
1250 (0dB gain)
1253 (-3dB gain)
1256 (-6dB gain)
Common Mode
All versions
Common Mode Rejection Ratio CMRR
Matched source impedances; V
CM
= ±10V
DC
60Hz
20kHz
Power Supply Rejection Ratio
6
Total Harmonic Distortion
Output Noise
PSRR
THD
e
OUT
±3V to ±18V; V
CC
= -V
EE
; all gains
40
40
—
—
50
50
50
90
—
—
—
—
dB
dB
dB
dB
—
—
—
—
18
21
24
18
—
—
—
—
kΩ
kΩ
kΩ
kΩ
Conditions
No signal
Min
—
6
—
—
—
—
—
—
Typ
2.0
—
21.5
24.4
27.5
27.5
29.1
31
Max
2.8
36
—
—
—
—
—
—
Units
mA
V
dBu
dBu
dBu
dBu
dBu
dBu
V
IN-CM
Input Impedance
5
Z
IN-DIFF
Z
IN-CM
V
IN_DIFF
= 10dBV, f = 1kHz, BW = 22kHz, R
L
= 2 kΩ
—
22 Hz to 22kHz bandwidth
1250 (0dB gain)
1253 (-3dB gain)
1256 (-6dB gain)
—
—
—
—
0.0006
—
%
-103
-105
-106
12
—
—
—
—
dBu
dBu
dBu
V/μs
Slew Rate
SR
R
L
= 2kΩ; C
L
= 300 pF, all gains
1. All specifications are subject to change without notice.
2. Unless otherwise noted, T
A
=25ºC, V
CC
=+15V, V
EE
= -15V.
3. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; the functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not impli ed. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
4. 0 dBu = 0.775 Vrms.
5. While specific resistor ratios are very closely trimmed, absolute resistance values can vary ±25% from the typical values show n. Input impedance is
monitored by lot sampling.
6. Defined with respect to differential gain.
7. Parameter guaranteed over the entire range of power supply and temperature.
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2008, THAT Corporation
THAT 1250 Series
Low-cost Balanced Line Receiver ICs
Page 3 of 8
Document 600068 Rev 02
Electrical Characteristics (con’t)
2,4
Parameter
Small signal bandwidth
Symbol
BW
-3dB
Conditions
R
L
= 2kΩ; C
L
= 10 pF
1250 (0dB gain)
1253 (-3dB gain)
1256 (-6dB gain)
f = 1 kHz
R
L
= 2kΩ; C
L
= 200 pF
R
L
= 2kΩ; C
L
= 200 pF
No signal
R
L
= 0
Ω
Min
—
—
—
-0.2
V
CC
-3
—
-10
—
—
Typ
8.6
12.2
18
0
V
CC
-2
V
EE
+2
—
±25
—
Max
—
—
—
+0.2
—
V
EE
+3
+10
—
200
Units
MHz
MHz
MHz
dB
V
V
mV
mA
pF
Output Gain Error
Output Voltage Swing
G
ER-OUT
V
O+
V
O-
V
OFF
I
SC
C
L
Output Offset Voltage
Output Short Circuit Current
Capacitive Load
7
V
CC
In-
R
1
b
R
2
Sense
~
½v
IN(DIFF)
½v
IN(DIFF)
Vout
~
In+
R
3
R
a
R
Ref
L
4
C
L
V
IN(CM)
~
V
EE
Figure 2. THAT 1250 series test circuit
Theory of Operation
The THAT 1250-series ICs consist of high
performance opamps with integrated, thin-film resis-
tors. These designs take full advantage of THAT fully
complementary dielectric isolation (DI) process to
deliver excellent performance with low current
consumption. The devices are simple to apply in
many applications.
trimming is performed.
As a result of their
monolithic construction, the R
3
/R
4
ratio generally
matches within ±0.5% of the R
1
/R
2
ratio. 0.5%
matching is about 50 dB CMRR for the 1256 and 52
dB for the 1250.
However, while the resistor ratios are tightly
controlled, the actual value of any individual resistor
is not. Lot-to-lot variations of up to ±30 % are to be
expected.
If higher CMRR is required in a simple input
stage, consider the THAT 1240-series ICs. These
parts are laser trimmed to improve the inherent
precision of our thin-film resistor process. For
Resistor Matching, Values, and CMRR
The 1250-series devices rely upon the inherent
matching of silicon-chromium (Si-Cr), thin-film,
integrated resistors to achieve a 50 dB common
mode rejection ratio and tight gain accuracy. No
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2008, THAT Corporation
Document 600068 Rev 02
Page 4 of 8
THAT 1250 Series
Low-cost Balanced Line Receiver ICs
demanding applications in which the source imped-
ance balance may be less than perfect, the 1200-
series ICs offer exceptional CMRR performance via a
patented method of increasing common-mode input
impedance.
THAT recommends dc-coupling the inputs of the
1250-series devices.
Input Voltage Limitations
When configured, respectively, for -3 dB and
-6 dB gain, the 1253 and 1256 devices are capable of
accepting input signals above the power supply rails.
This is because the internal opamp’s inputs connect
to the outside world only through the on-chip resis-
tors R
1
through R
4
at nodes a and b as shown in
Figure 2. Consider the following analysis.
Input Considerations
The 1250-series devices are internally protected
against input overload via an unusual arrangement of
diodes connecting the + and - Input pins to the
power supply pins. The circuit of Figure 3 shows the
arrangement used for the R
3
/ R
4
side; a similar one
applies to the other side. The zener diodes prevent
the protection network from conducting until an
input pin is raised at least 50 V above V
CC
or below
V
EE
. Thus, the protection networks protect the
devices without constraining the allowable signal
swing at the input pins. The reference (and sense)
pins are protected via more conventional reverse-
biased diodes which will conduct if these pins are
raised above V
CC
or below V
EE
.
Because the 1250-series devices are input
stages, their input pins are of necessity connected to
the outside world. This is likely to expose the parts
to ESD when cables are connected and disconnected.
Our testing indicates that the 1250-series devices will
typically withstand application of up to 1,000 volts
under the human body ESD model.
To reduce risk of damage from ESD, and to
prevent RF from reaching the devices, THAT recom-
mends the circuit of Figure 4. C
3
through C
5
should
be located close to the point where the input signal
comes into the chassis, preferably directly on the
input connector. The unusual circuit design
minimizes the unbalancing impact of differences in
the values of C
4
and C
5
by forcing the capacitance
from each input to chassis ground to depend primar-
ily on the value of C
3
. The circuit shown is approxi-
mately ten times less sensitive to mismatches
between C
4
and C
5
than the more conventional
approach in which the junction of C
4
and C
5
is
grounded directly
6
.
Designers frequently seek to improve RF bypass-
ing through the addition of R-C networks at the
inputs (series resistor followed by a capacitor to
ground at each input). Generally, THAT recommends
keeping any such series resistances under 50W, so
as not to upset the intrinsic balance between the
1250’s internal R
1
/R
2
and R
3
/R
4
resistor ratios.
Because the internal resistor absolute values are not
well controlled, the external resistors can interact
with the internal ones in unexpected ways. As an
alternative to a resistor as additional build-out
impedance, THAT recommends the use of a ferrite
bead or balun instead.
If it is necessary to ac-couple the inputs of the
1250-series parts, the coupling capacitors should be
sized to present negligible impedance at any frequen-
cies of interest for common mode rejection. Regard-
less of the type of coupling capacitor chosen,
variations in the values of the two capacitors,
working against the 1250-series input impedance,
can unbalance common mode input signals, convert-
ing them to balanced signals which will not be
rejected by the CMRR of the devices. For this reason,
Differential Input Signals
For differential signals (v
IN(DIFF)
), the limitation to
signal handling will be output clipping. The outputs
of all the devices typically clip at within 2V of the
supply rails. Therefore, maximum differential input
signal levels are directly related to the gain and
supply rails.
Common-mode Input Signals
For common-mode input signals, there is very
little output signal. The limitation on common-mode
handling is the point at which the inputs are
overloaded. So, we must consider the inputs of the
opamp.
For common-mode signals (V
IN(CM)
), the common-
mode input current splits to flow through both R
1
/R
2
and through R
3
/R
4
. Because v
b
is constrained to
follow V
a
, we will consider only the voltage at node a.
The voltage at a can be calculated as:
v
a
=
v
IN(CM)
v
IN(CM)
=
v
a
R
4
R
3
+R
4
R
3
+R
4
R
4
.
Again, solving for V
IN(CM)
,
.
For the 1250, (R
3
+ R
4
) / R
4
= 2. For the 1253,
(R
3
+ R
4
) / R
4
= 2.4. For the 1256, (R
3
+ R
4
) / R
4
=3.
Furthermore, the same constraints apply to Va as in
the differential analysis.
Following the same reasoning as above, the
maximum common-mode input signal for the 1250 is
(2V
CC
- 4) V, and the minimum is (2V
EE
+ 4) V. For
the 1253, these figures are (2.4V
CC
- 4.8) V, and
(2.4V
EE
+ 4.8) V. For the 1256, these figures are
(3V
CC
- 6) V, and (3V
EE
+ 6) V.
Therefore, for common-mode signals and ±15 V
rails, the 1250 will accept up to ~26 V in either
direction. As an ac signal, this is 52 V peak-peak,
18.4 V rms, or +27.5 dBu. With the same supply
rails, the 1253 will accept up to ~31 V in either
direction. As an ac signal, this is 62 V peak-peak,
21.9 V rms, or +29 dBu. With the same supply rails,
the 1256 will accept up to ~39 V in either direction.
As an ac signal, this is 78 V peak-peak, 27.6 V rms,
or +31 dBu.
Of course, in the real world, differential and
common-mode signals combine. The maximum
signal that can be accommodated will depend on the
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2008, THAT Corporation
THAT 1250 Series
Low-cost Balanced Line Receiver ICs
Page 5 of 8
Document 600068 Rev 02
-
V
CC
capacitors should be located within a few inches of
the supply pins on these parts, as shown in Figure 4.
+
V
CC
Selecting a Gain Variation
The three different parts offer different gain
structures to suit different applications. The 1256 is
customarily configured for -6 dB gain, but by revers-
ing the resistor connections, can also be configured
for +6 dB. The 1253 is most often configured for -3
dB gain, but can also be configured for +3 dB. The
choice of input gain is determined by the input
voltage range to be accommodated, and the power
supply voltages used within the circuit.
To minimize noise and maximize signal-to-noise
ratio, the input stage should be selected and config-
ured for the highest possible gain that will ensure
that maximum-level input signals will not clip the
input stage or succeeding stages. For example, with
±18 V supply rails, the 1250-series parts have a
maximum output signal swing of +23 dBu. In order
to accommodate +24 dBu input signals, the
maximum gain for the stage is -1 dB. With ±15 V
supply rails, the maximum output signal swing is
~+21.1 dBu; here, -3 dB is the maximum gain. In
each case, a 1253 configured for -3 dB gain is the
ideal choice. The 1250 (0dB gain only) will not
provide enough headroom at its output to support a
+24 dBu input signal. The 1256 (configured for -6
dB gain) will increase noise, thus reducing dynamic
range, by attenuating the input signal more than
necessary to support a +24 dBu input.
In fact, for most professional audio applications,
THAT recommends the -3 dB input configuration
possible only with the 1253 in order to preserve
dynamic range within a reasonable range of power
supply voltages and external headroom limits.
In+
R
3
R
4
V
EE
V
EE
Ref
Figure 3. Representative input protection circuit
superposition of both differential and common-
mode limitations.
Output Considerations
The 1250-series devices are typically capable of
supplying 25 mA into a short circuit. While they will
survive a short, power dissipation will rise dramati-
cally if the output is shorted. Junction temperature
must be kept under 125 ºC to maintain the devices’
specifications.
These devices are stable with up to 300 pF of
load capacitance.
Power Supply Considerations
The 1250-series parts are not particularly sensi-
tive to the power supply, but they do contain wide
bandwidth opamps. Accordingly, small local bypass
V
CC
C2
In-
C4
470p
C5
470p
100n
2
In-
7
7
U1
THAT1250
9k
Sense
6
Vout
5
-In
2
In-
9k
V
CC
C3
47p
5
V
CC
Sens
6
Out
Ref
V
EE
3
1
In+
U1
4
Out
Output
THAT1256/1253/1250
In+
C1
100n
V
EE
+In
3
In+
9k
V
EE
4
9k
Ref
1
Figure 4. RFI and supply bypassing
Figure 5. Zero dB line receiver
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com
Copyright © 2008, THAT Corporation
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
