®
ISL12029, ISL12029A
Data Sheet
December 16, 2010
FN6206.10
Real Time Clock/Calendar with I
2
C Bus™
and EEPROM
The ISL12029 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (open drain
output), intelligent battery backup switching, CPU
Supervisor, integrated 512x8-bit EEPROM configured in 16
bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12029 and ISL12029A Power Control Settings are
different. The ISL12029 uses the Legacy Mode Setting, and
the ISL12029A uses the Standard Mode Setting.
Applications that have V
BAT
> V
DD
will require only the
ISL12029A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I
2
C
Communications During Battery Backup” on page 24 for
important details.
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation:
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions
- Power-On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s, 1.5s)
• I
2
C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Pinout
ISL12029, ISL12029A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
V
BAT
IRQ/F
OUT
NC
NC
SCL
SDA
NC = No internal connection
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Utility Meters
HVAC Equipment
Audio/Video Components
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/AutomotivePAR
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I
2
C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2010.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL12029, ISL12029A
Block Diagram
OSC COMPENSATION
32.768kHZ
X1
OSCILLATOR
X2
IRQ/F
OUT
SCL
SDA
SELECT
CONTROL
SERIAL
INTERFACE DECODE
LOGIC
DECODER
CONTROL/
REGISTERS
(EEPROM)
STATUS
REGISTERS
(SRAM)
COMPARE
MASK
ALARM REGS
(EEPROM)
4k
EEPROM
ARRAY
TIMER
FREQUENCY 1Hz
CALENDAR
DIVIDER
LOGIC
TIME
KEEPING
REGISTERS
(SRAM)
BATTERY
SWITCH
CIRCUITRY
V
DD
V
BACK
ALARM
8
RESET
WATCHDOG
TIMER
LOW VOLTAGE
RESET
Pin Descriptions
PIN
NUMBER
1
2
6
SYMBOL
X1
X2
RESET
DESCRIPTION
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
RESET. This is a reset signal output. This signal notifies a host processor that the “Watchdog” time period has
expired or that the voltage has dropped below a fixed V
TRIP
threshold. It is an open drain active LOW output.
Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground.
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is
always active (not gated).
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. It
is an open drain output. The function is set via the configuration register.
This input provides a backup supply voltage to the device. V
BAT
supplies power to the device in the event that the
V
DD
supply fails. This pin should be tied to ground if not used.
Power Supply.
No Internal Connection.
7
8
9
12
13
14
3, 4, 5, 10,
11
GND
SDA
SCL
IRQ/F
OUT
V
BAT
V
DD
NC
2
FN6206.10
December 16, 2010
ISL12029, ISL12029A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL12029IB27Z
ISL12029IB27AZ
ISL12029IB30AZ
ISL12029IBZ
ISL12029IBAZ
ISL12029IV27Z
ISL12029IV27AZ
ISL12029IV30AZ
ISL12029IVZ
ISL12029IVAZ
ISL12029AIB27Z
ISL12029AIV27Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL12029, ISL12029A.
For more information on MSL please see
techbrief
TB363.
V
BAT
TRIP POINT
PART MARKING
(V)
12029IB27Z
12029IB27 AZ
12029IB30 AZ
12029IBZ
12029IBAZ
12029 IV27Z
12029 27AZ
12029 30AZ
12029 IVZ
12029 IVAZ
12029AIB 27Z
2029A IV27Z
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
V
DD
< V
BAT
2.2
2.2
BSW BIT
DEFAULT
SETTING
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 1
BSW = 0
BSW = 0
V
RESET
VOLTAGE
(V)
2.63
2.92
3.09
4.38
4.64
2.63
2.92
3.09
4.38
4.64
2.63
2.63
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld SOIC
14 Ld TSSOP
PKG. DWG. #
M14.15
M14.15
M14.15
M14.15
M14.15
M14.173
M14.173
M14.173
M14.173
M14.173
M14.15
M14.173
3
FN6206.10
December 16, 2010
ISL12029, ISL12029A
Absolute Maximum Ratings
Voltage on V
DD
, V
BAT
, SCL, SDA, and IRQ/F
OUT
Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 Pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model (MIL-STD-883, Method 3014) . . . . . . .>±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
14 Ld SOIC Package (Notes 5, 6) . . . .
90
40
14 Ld TSSOP Package (Note 5, 6) . . .
110
35
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For
θ
JC
, the “case temp” location is taken at the package top center.
DC Electrical Specifications
Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are at T
A
= +25°C
and V
DD
= 3.3V.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 16)
2.7
1.8
MAX
(Note 16)
5.5
5.5
SYMBOL
V
DD
V
BAT
PARAMETER
Main Power Supply
Backup Power Supply
CONDITIONS
TYP
UNIT
V
V
NOTES
Electrical Specifications
SYMBOL
I
DD1
Boldface limits apply over the operating temperature range, -40°C to +85°C.
CONDITIONS
V
DD
= 2.7V
V
DD
= 5.5V
MIN
(Note 16)
TYP
MAX
(Note 16)
500
800
2.5
3.5
10
20
800
850
-100
1.8
2.2
30
50
10
1000
1200
100
2.6
UNIT
µA
µA
mA
mA
µA
µA
nA
nA
nA
V
mV
mV
V/ms
11
11, 13
11, 13
12
7, 10, 11
7, 8, 9
NOTES
7, 8, 9
PARAMETER
Supply Current with I
2
C Active
I
DD2
Supply Current for Non-Volatile
Programming
Supply Current for Main
Timekeeping (Low Power Mode)
Battery Supply Current
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= V
SDA
= V
SCL
= 2.7V
V
DD
= V
SDA
= V
SCL
= 5.5V
V
BAT
= 1.8V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0V
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= V
RESET
= 0V
,
9
I
DD3
I
BAT
I
BATLKG
V
TRIP
V
TRIPHYS
V
BATHYS
V
DD SR-
Battery Input Leakage
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
V
DD
Negative Slew Rate
V
DD
= 5.5V, V
BAT
= 1.8V
IRQ/F
OUT,
RESET OUTPUTS
V
OL
Output Low Voltage
V
DD
= 5.5V
I
OL
= 3mA
V
DD
= 2.7V
I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
4
FN6206.10
December 16, 2010
ISL12029, ISL12029A
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
t
RPD
t
PURST
V
RVALID
V
RESET
PARAMETER
V
DD
Detect to RESET LOW
Power-Up Reset Time-Out Delay
Minimum VDD for Valid RESET
Output
ISL12029-4.5A Reset Voltage Level
ISL12029 Reset Voltage Level
ISL12029-3 Reset Voltage Level
ISL12029-2.7A Reset Voltage Level
ISL12029-2.7 Reset Voltage Level
t
WDO
Watchdog Timer Period
32.768kHz crystal between X1
and X2
100
1.0
4.59
4.33
3.04
2.87
2.58
1.70
725
225
t
RST
t
RSP
Watchdog Timer Reset Time-Out
Delay
I
2
C Interface Minimum Restart Time
32.768kHz crystal between X1
and X2
225
1.2
4.64
4.38
3.09
2.92
2.63
1.75
750
250
250
4.69
4.43
3.14
2.97
2.68
1.801
775
275
275
CONDITIONS
MIN
(Note 16)
TYP
(Note 11)
500
250
400
MAX
(Note 16)
UNITS
ns
ms
V
V
V
V
V
V
s
ms
ms
ms
µs
NOTES
13
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature
≤ +75°C
>2,000,000
50
Cycles
Years
Serial Interface (I
2
C) Specifications - DC/AC Characteristics
SYMBOL
V
IL
V
IH
PARAMETER
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
CONDITIONS
SBIB = 1 (Under V
DD
mode)
SBIB = 1 (Under V
DD
mode)
SBIB = 1 (Under V
DD
mode)
I
OL
= 4mA
V
IN
= 5.5V
V
IN
= 5.5V
MIN
(Note 16)
-0.3
0.7 x V
DD
0.05 x V
DD
0
0.1
0.1
0.4
10
10
TYP
MAX
(Note 16)
0.3 x V
DD
V
DD
+ 0.3
UNITS
V
V
V
V
µA
µA
NOTES
Hysteresis SDA and SCL Input Buffer
Hysteresis
V
OL
I
LI
I
LO
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
TIMING CHARACTERISTICS
f
SCL
t
IN
t
AA
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Any pulse narrower than the max
spec is suppressed.
SCL falling edge crossing 30% of
V
DD
, until SDA exits the 30% to
70% of V
DD
window.
SDA crossing 70% of V
DD
during
a STOP condition, to SDA
crossing 70% of V
DD
during the
following START condition.
Measured at the 30% of V
DD
crossing.
1300
400
50
900
kHz
ns
ns
t
BUF
ns
t
LOW
Clock LOW Time
1300
ns
5
FN6206.10
December 16, 2010
微控制器 MCU
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