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CY7C1021CV33-12ZSXET

产品描述SRAM 2Mb 3.3V 12ns 64Kx16 Fast Async SRAM
产品类别存储   
文件大小508KB,共19页
制造商Cypress(赛普拉斯)
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CY7C1021CV33-12ZSXET概述

SRAM 2Mb 3.3V 12ns 64Kx16 Fast Async SRAM

CY7C1021CV33-12ZSXET规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
Cypress(赛普拉斯)
产品种类
Product Category
SRAM
RoHSDetails
Memory Size1 Mbit
Organization64 k x 16
Access Time12 ns
接口类型
Interface Type
Parallel
电源电压-最大
Supply Voltage - Max
3.63 V
电源电压-最小
Supply Voltage - Min
2.97 V
Supply Current - Max90 mA
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TSOP-44
系列
Packaging
Cut Tape
系列
Packaging
MouseReel
系列
Packaging
Reel
数据速率
Data Rate
SDR
Memory TypeSDR
类型
Type
Asynchronous
Number of Ports1
Moisture SensitiveYes
工厂包装数量
Factory Pack Quantity
1000

文档预览

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CY7C1021CV33 Automotive
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O
1
through I/O
8
)
[1]
, is written into
the location specified on the address pins (A
0
through A
15
). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O
9
through I/O
16
)
[1]
is written into the location specified on the
address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O
1
to I/O
8 [1]
. If Byte High Enable (BHE) is LOW, then data
from memory appears on I/O
9
to I/O
16 [1]
. For more information,
see the
Truth Table on page 11
for a complete description of
Read and Write modes.
The input and output pins (I/O
1
through I/O
16
) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For a complete list of related documentation,
click here.
Temperature ranges
Automotive-A: –40 °C to 85 °C
Automotive-E: –40 °C to 125 °C
Pin and function compatible with CY7C1021CV33
High speed
t
AA
= 10 ns (Automotive-A)
t
AA
= 12 ns (Automotive-E)
CMOS for optimum speed and power
Low active power: 325 mW (max)
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II, and 48-ball FBGA packages
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
[1]
I/O
8
–I/O
15
[1]
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. I/O
1
–I/O
16
for SOJ/TSOP and I/O
0
–I/O
15
for BGA packages.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *Q
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised December 2, 2014

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