MB39A136
2ch PFM/PWM DC/DC Converter IC with
Synchronous Rectification
MB39A136 is 2ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification method. It contains the
enhanced protection features, and supports the symmetrical-phase method and the ceramic capacitor. MB39A136 realizes rapid
response, high efficiency, and low ripple voltage, and its high-frequency operation enables the miniaturization of inductors and I/O
capacitors.
Features
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High efficiency
For frequency setting by external resistor : 100 kHz to 1 MHz
Error Amp threshold voltage
Minimum output voltage value
Wide range of power-supply voltage
Supports Symmetrical-Phase method
With built-in over voltage protection function
With built-in under voltage protection function
With built-in over current protection function
With built-in over-temperature protection function
With built-in soft start/stop circuit without load dependence
With built-in synchronous rectification type output steps for N-ch MOS FET
Standby current
Small package
: 0 [
A] Typ
: TSSOP-24
: 0.7 V
1.0
: 0.7 V
: 4.5 V to 25 V
PFM/PWM auto switching mode and fixed PWM mode selectable
Application
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Digital TV
Photocopiers
Surveillance cameras
Set-top boxes (STB)
DVD players, DVD recorders
Projectors
IP phones
Vending machine
Consoles and other non-portable devices
Cypress Semiconductor Corporation
Document Number: 002-08376 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 22, 2016
MB39A136
Contents
Pin Assignment ................................................................ 3
Pin Description ................................................................. 4
Block Diagram .................................................................. 5
Absolute Maximum Ratings ............................................ 6
Recommended Operating Conditions ............................ 7
Electrical Characteristics ................................................. 8
Typical Characteristics .................................................. 12
Function Description ...................................................... 14
Current Mode ............................................................ 14
Protection Function Table ............................................. 18
I/O Pin Equivalent Circuit Diagram ............................... 19
Example Application Circuit .......................................... 21
Parts List ......................................................................... 22
Application Note ............................................................. 24
Reference Data ............................................................... 41
Usage Precaution ........................................................... 43
Ordering Information ...................................................... 44
EV Board Ordering Information ................................. 44
RoHS Compliance Information Of
Lead (Pb) Free Version .................................................. 45
Marking Format (Lead Free version) ......................... 45
Labeling Sample (Lead free version) ....................... 46
MB39A136PFT Recommended Conditions
Of Moisture Sensitivity Level ........................................ 47
Package Dimensions ...................................................... 48
Major Changes ................................................................ 49
Document Number: 002-08376 Rev. *A
Page 2 of 50
MB39A136
1. Pin Assignment
(TOP VIEW)
CTL1
CS1
FB1
COMP1
ILIM1
RT
VREF
CTL2
ILIM2
COMP2
FB2
CS2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CB1
DRVH1
LX1
DRVL1
VCC
VB
GND
DRVL2
LX2
DRVH2
CB2
MODE
(FPT-24P-M09)
Document Number: 002-08376 Rev. *A
Page 3 of 50
MB39A136
2. Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
CTL1
CS1
FB1
COMP1
ILIM1
RT
VREF
CTL2
ILIM2
COMP2
FB2
CS2
MODE
CB2
DRVH2
LX2
DRVL2
GND
VB
VCC
DRVL1
LX1
DRVH1
CB1
I
I
I
O
I
I/O
CH1 control pin.
CH1 soft-start time setting capacitor connection pin.
CH1 Error amplifier inverted input pin.
CH1 error amplifier output pin.
CH1 over current detection level setting voltage input pin.
Oscillation frequency setting resistor connection pin.
Reference voltage output pin.
CH2 control pin.
CH2 over current detection level setting voltage input pin.
CH2 error amplifier output pin.
CH2 Error amplifier inverted input pin.
CH2 soft-start time setting capacitor connection pin.
PFM/PWM switch pin. (CH1 and CH2 commonness) It becomes fixed PWM operation with
the VREF connection, and it becomes PFM/PWM operation with the GND connection.
CH2 connection pin for boot strap capacitor.
CH2 output pin for external high-side FET gate drive.
CH2 inductor and external high-side FET source connection pin.
CH2 output pin for external low-side FET gate drive.
Ground pin.
Bias voltage output pin.
Power supply pin for reference voltage and control circuit.
CH1 output pin for external low-side FET gate drive.
CH1 inductor and external high-side FET source connection pin.
CH1 output pin for external high-side FET gate drive.
CH1 connection pin for boot strap capacitor.
Description
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O
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O
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Document Number: 002-08376 Rev. *A
Page 4 of 50
MB39A136
3. Block Diagram
MODE
13
<CH1>
<Soft-Start,
Soft-Stop>
RT
6
20
VCC
VREF
5.5
μA
70 kΩ
<PFM Comp. >
+
pfm1
−
CS1
2
ctl1
/uvp_out
/otp_out
/uvlo
ovp_out
Clock
generator
pfm2
Bias
Reg.
19
VB
2.0 V
ch.1
ch.2
180° out of phase
CB1
DRVH1
LX1
COMP1
4
<Error Amp>
3
−
+
+
Hi-side
Drive
24
23
FB1
<I Comp.>
−
+
RS-FF
RQ
S
CLK
intref
ILIM1
5
Vs
<OVP Comp.>
Drive
Logic
22
VB
21
Lo-side
Drive
<Di Comp.>
Level
Converter
−
+
DRVL1
+
−
<UVP Comp.>
−
+
intref
x 1.15 V
ovp1
ovp1
ovp2
uvp1
uvp2
50
μs
delay
512/f
OSC
delay
intref
x 0.7 V
uvp1
<UVLO>
SQ
R
SQ
R
uvp_out
ovp_out
uvlo
H:UVLO
release
otp_out
VB
UVLO
VREF
UVLO
OTP
14
15
16
CB2
DRVH2
LX2
CS2
12
<CH2>
The configuration of a control circuit is the same as that of CH1.
COMP2
10
FB2
11
17
VB ctl1, ctl2
DRVL2
ILIM2
9
<REF> <CTL>
intref
(3.3 V)
7
VREF
ON/OFF
CTL1
1
8 CTL2
18
GND
Document Number: 002-08376 Rev. *A
Page 5 of 50
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