DATASHEET
ISL6424
Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6424 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I
2
C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I
2
C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I
2
C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I
2
C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin allows the 13V to 18V
transition with an external pin, overriding the I
2
C input.
The ISL6424 is offered in a 32 Ld 5x5 QFN.
FN9175
Rev 3.00
Sep 13, 2005
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I
2
C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• I
2
C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V/5V Operation up to 400kHz
• External Pins to Select 13V/18V Option
• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I
2
C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
Ordering Information
PART # *
ISL6424ER
PART
MARKING
ISL6424ER
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN L32.5x5
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN9175 Rev 3.00
Sep 13, 2005
Page 1 of 13
ISL6424
Absolute Maximum Ratings
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN 1&2, SEL18V 1&2) . . . . . . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2)
JA
(°C/W)
JC
(°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . -20°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. The device junction temperature should be kept below 150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
V
CC
= 12V, T
A
= -20°C to +85°C, unless otherwise noted. Typical values are at T
A
= 25°C. EN1 = EN2 = H,
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I
2
C access to the system.
SYMBOL
TEST CONDITIONS
MIN
8
EN1 = EN2 = L
I
IN
EN1 = EN2 = LLC1 = LLC2 = VSEL1 =
VSEL2 = ENT1 = ENT2 = H, No Load
-
-
TYP
12
1.5
4.0
MAX
14
3.0
8.0
UNITS
V
mA
mA
PARAMETER
Operating Supply Voltage Range
Standby Supply Current
Supply Current
UNDERVOLTAGE LOCKOUT
Start Threshold
Stop Threshold
Start to Stop Hysteresis
SOFT-START
COMP Rise Time (Note 4)
Output Voltage (Note 5)
7.5
7.0
350
-
-
400
7.95
7.55
500
V
V
mV
(Note 5)
V
O1
V
O1
V
O1
V
O1
V
O2
V
O2
V
O2
V
O2
VSEL1 = L, LLC1 = L
VSEL1 = L, LLC1 = H
VSEL1 = H, LLC1 = L
VSEL1 = H, LLC1 = H
VSEL2 = L, LLC2 = L
VSEL2 = L, LLC2 = H
VSEL2 = H, LLC2 = L
VSEL2 = H, LLC2 = H
V
IN
= 8V to 14V; V
O1
, V
O2
= 13V
V
IN
= 8V to 14V; V
O1
, V
O2
= 18V
I
O
= 12mA to 350mA
I
O
= 12mA to 750mA (Note 6)
DCL = L, ISEL1/2 = L
DCL = L, ISEL1/2 = H (Note 6)
-
12.74
13.72
17.64
18.62
12.74
13.72
17.64
18.62
-
-
-
-
425
775
-
-
512
13.0
14.0
18.0
19.0
13.0
14.0
18.0
19.0
4.0
4.0
50
100
-
850
900
20
-
13.26
14.28
18.36
19.38
13.26
14.28
18.36
19.38
40.0
60.0
80
200
550
950
-
-
Cycles
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mA
mA
ms
ms
Line Regulation
DV
O1,
DV
O2
DV
O1,
DV
O2
I
MAX
Load Regulation
Dynamic Output Current Limiting
Dynamic Overload Protection Off Time
Dynamic Overload Protection On Time
TOFF
TON
DCL = L, Output Shorted (Note 6)
FN9175 Rev 3.00
Sep 13, 2005
Page 5 of 13
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