time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com
Rev. C, 05/20/2015
3
IS31LT3938
ABSOLUTE MAXIMUM RATINGS (Note 1)
VIN, GATE pin to GND
DIM1,DIM2,CS, ADJ, TOFF pin to GND
VIN pin input current (Note 2)
Operating temperature (T
A
=T
J
)
Junction temperature
Device storage temperature
ESD (HBM)
ESD (CDM)
-0.3V ~ 13.0V
-0.3V ~ 6.0V
10mA
-40
o
C ~ +125
o
C
-40
o
C ~ +150
o
C
-65
o
C ~ +150
o
C
4kV
1kV
Note 1:
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Note 2:
Beyond the input current range, VIN pin may not clamp at 9V (Typ.).
ELECTRICAL CHARACTERISTICS
The specifications are at T
A
=25°C and V
IN
=20V (Note 3), R
IN
=1.5kΩ, C
IN
=10µF unless otherwise noted. (Note 4)
Symbol
V
IN
Parameter
Input DC supply voltage range
Conditions
Supply voltage connected to
VIN via an appropriate
resistor
V
IN
falling
V
IN
=V
CLAMP
, Gate floating
V
IN
= UVLO
245
V
CS
=V
CS_TH
+50mV
R
EXT
=250kΩ
9.8
Min.
10
8
9
7
1.6
450
200
250
500
10
2.5
0.5
0.5
2.5
C
GATE
=1nF
C
GATE
=1nF
60
50
150
20
0.4
2.5
4
4
6
80
80
10.2
700
350
255
Typ.
Max.
450
10
Unit
V
V
V
V
µA
µA
mV
ns
µs
V
V
V
V
ns
ns
o
o
V
CLAMP
VIN pin clamp voltage
UVLO
I
IN
I
IN,UV
V
CS_TH
t
BLANK
t
OFF
Undervoltage lockout
Quiescent current
Input current in UVLO
Peak current sense threshold
Current sense blanking time
Off time
PWM input voltage high threshold
V
ADJ
PWM input voltage low threshold
(Note 5) Linear dimming off output threshold
Linear dimming full output threshold
t
R
t
f
T
P
△
T
P
△
UVLO UVLO hysteresis
GATE rises from 0.1×V
CLAMP
to
0.9×V
CLAMP
GATE falls from 0.9× V
CLAMP
to 0.1×
V
CLAMP
Over temperature protection threshold
Over temperature protection hysteresis
Over current protection CS voltage
threshold
Maximum switch off time for power
sequencing
C
C
V
OCP
V
ms
s
t
OFF_RESET
Over current protection t
OFF
delay time
t
MAX
Note 3:
V
IN
is the input voltage. When V
IN
>9V, input voltage connected to VIN pin should via a appropriate resistor.
Note 4:
Production testing of the chip is performed at 25°C. Functional operation of the chip and parameters specified are guaranteed by design,
characterization and process control in other temperature
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
