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74VCXH16245TTR

产品描述Bus Transceivers 16-Bit Transceiver
产品类别逻辑    逻辑   
文件大小286KB,共11页
制造商ST(意法半导体)
官网地址http://www.st.com/
标准
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74VCXH16245TTR概述

Bus Transceivers 16-Bit Transceiver

74VCXH16245TTR规格参数

参数名称属性值
是否Rohs认证符合
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
Reach Compliance Codecompliant
控制类型COMMON CONTROL
计数方向BIDIRECTIONAL
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
JESD-609代码e4
长度12.5 mm
负载电容(CL)30 pF
逻辑集成电路类型BUS TRANSCEIVER
最大I(ol)0.024 A
湿度敏感等级3
位数8
功能数量2
端口数量2
端子数量48
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源3.3 V
Prop。Delay @ Nom-Sup3.1 ns
传播延迟(tpd)3.8 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.3 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层NICKEL PALLADIUM GOLD
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
翻译N/A
宽度6.1 mm
Base Number Matches1

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74VCXH16245
LOW VOLTAGE CMOS 16-BIT BUS TRANSCEIVER
(3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
PD
= 2.5 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.2 ns (MAX.) at V
CC
= 2.3 to 2.7V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 18mA (MIN) at V
CC
= 2.3V
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.8V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H16245
BUS HOLD PROVIDED ON BOTH SIDES
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
74VCXH16245TTR
PIN CONNECTION
O
DESCRIPTION
The 74VCXH16245 is a low voltage CMOS 16 BIT
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and five-layer metal wiring
C
2
MOS technology. It is ideal for low power and
very high speed 2.3 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable
the device so that the buses are effectively
isolated.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
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T&R
July 2003
1/11

 
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