Lead-
Free
Package
Options
Available!
ispLSI 2032/A
In-System Programmable High Density PLD
Functional Block Diagram
®
Features
• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
N
S
A7
Output Routing Pool (ORP)
Select devices have been discontinued.
See Ordering Information section for product status.
A0
Output Routing Pool (ORP)
—
—
—
—
—
1000 PLD Gates
32 I/O Pins, Two Dedicated Inputs
32 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
—
—
—
—
—
—
Input Bus
A2
GLB
Logic
Array
D Q
D Q
A5
D Q
f
max
= 180 MHz Maximum Operating Frequency
t
pd
= 5.0 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
N
EW
A3
A4
0139Bisp/2000
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
LS
I2
03
2E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
U
SE
is
p
FO
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
R
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
2032_11
1
Input Bus
A1
D
ES
IG
D Q
Global Routing Pool
(GRP)
A6
Specifications
ispLSI 2032/A
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
GOE 0
N
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
S
Select devices have been discontinued.
See Ordering Information section for product status.
A0
A7
A1
Input Bus
EW
N
Y0
Y1*/RESET
Input Bus
Global Routing Pool
(GRP)
A6
A2
A5
A3
R
A4
FO
MODE
ispEN
Notes:
*Y1 and RESET are multiplexed on the same pin
03
2E
SCLK/Y2
0139B(1)isp/2000
I2
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
U
SE
The devices also have 32 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
is
p
LS
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032 and 2032A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
2
CLK 0
CLK 1
CLK 2
D
ES
IG
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
Specifications
ispLSI 2032/A
Absolute Maximum Ratings
1
Supply Voltage V
cc
...................................-0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
N
EW
D
ES
IG
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
cc
+1
UNITS
V
V
V
V
Table 2 - 0005/2032
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
S
Select devices have been discontinued.
See Ordering Information section for product status.
T
A
= -40°C to + 85°C
Storage Temperature ................................ -65 to 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
V
CC
V
IL
V
IH
Capacitance (T
A
=25°C, f=1.0 MHz)
SYMBOL
03
2E
TYPICAL
6
7
10
FO
UNITS
pf
pf
pf
R
N
T
A
= 0°C to + 70°C
PARAMETER
Dedicated Input Capacitance
TEST CONDITIONS
V
CC
= 5.0V, V
IN
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2-0006/2032
Data Retention Specifications
is
p
Data Retention
SE
PARAMETER
LS
C
1
C
2
C
3
I/O Capacitance
Clock Capacitance
I2
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2-0008A-isp
Erase/Reprogram Cycles
U
3
Specifications
ispLSI 2032/A
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
-135, -150, -180
-80, -110
1.5V
1.5V
See Figure 2
Table 2-0003/2032
Figure 2. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
≤
1.5 ns
≤
3 ns
N
0213A
S
Select devices have been discontinued.
See Ordering Information section for product status.
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
–
–
–
V
V
μA
μA
μA
μA
mA
mA
mA
mA
Table 2-0007/2032
Output Load Conditions (see Figure 2)
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
Table 2 - 0004A
*
CL includes Test Fixture and Probe Capacitance.
C
DC Electrical Characteristics
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Over Recommended Operating Conditions
FO
R
N
EW
CONDITION
MIN.
–
2.4
–
–
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
60
40
40
3
LS
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2, 4
Input or I/O High Leakage Current 3.5V
≤
V
IN
≤
V
CC
ispEN Input Low Leakage Current 0V
≤
V
IN
≤
V
IL
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
-180, -150
V
IL
= 0.0V, V
IH
= 3.0V Comm.
Others
f
TOGGLE
= 1 MHz
Industrial
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I
CC
.
U
SE
is
p
I2
03
2E
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
4
D
ES
IG
Specifications
ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
1
2
3
4
5
6
7
8
9
4
DESCRIPTION
1
-180
–
–
180
5.0
7.5
–
–
–
–
–
–
–
–
–
–
-150
5.5
8.0
–
–
–
–
–
–
-135
7.5
10.0
–
–
–
–
4.5
–
–
5.5
–
10.0
–
12.0
12.0
6.0
6.0
–
–
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2E
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay
Clk Frequency with Internal Feedback
3
Clk Frequency with Ext. Feedback
Clk Frequency, Max. Toggle
GLB Reg Setup Time before Clk, 4 PT Bypass
GLB Reg. Clk to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk, 4 PT Bypass
GLB Reg. Setup Time before Clk
154
111
167
3.0
–
137
100
167
4.0
–
0.0
5.5
–
0.0
–
5.0
–
–
–
–
3.0
3.0
(
1
tsu2 + tco1
)
125
200
3.0
–
0.0
4.0
–
0.0
–
–
–
–
–
2.5
2.5
4.0
N
S
Select devices have been discontinued.
See Ordering Information section for product status.
4.0
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
4.5
7.0
EW
N
R
–
–
10.0
10.0
5.0
5.0
FO
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
U
SE
is
p
LS
I2
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
D
ES
IG
4.5
–
–
–
8.0
–
11.0
11.0
5.0
5.0
–
–
0.0
4.5
–
5.0
0.0
–
4.5
–
–
–
–
3.0
3.0
Table 2-0030B-180/2032
嵌入式系统
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