b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation
process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder intercon-
nection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71144
S-21251—Rev. B, 05-Aug-02
www.vishay.com
2-1
Si5435DC
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State
Drain Source On State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
r
DS( )
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= --250
mA
V
DS
= 0 V, V
GS
=
20
V
V
DS
= --24 V, V
GS
= 0 V
V
DS
= --24 V, V
GS
= 0 V, T
J
= 85_C
V
DS
--5
V, V
GS
= --10 V
V
GS
= --10 V, I
D
= --4.1 A
V
GS
= --4.5 V, I
D
= --3.1 A
V
DS
= --15 V, I
D
= --4.1 A
I
S
= --1.1 A, V
GS
= 0 V
--30
0.042
0.070
8
--0.8
--1.2
0.050
0.080
--1
100
--1
--5
V
nA
mA
A
Ω
S
V
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= --1.1 A, di/dt = 100 A/ms
V
DD
= --15 V, R
L
= 15
Ω
I
D
≅
--1 A, V
GEN
= --10 V, R
G
= 6
Ω
V
DS
= --15 V, V
GS
= --10 V, I
D
= --4.1 A
16
3.6
3.1
11
5
40
20
30
20
10
80
40
60
ns
24
nC
Notes
a. Pulse test; pulse width
≤
300
ms,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
