DATASHEET
ISL95712
Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0
The
ISL95712
is fully compliant with AMD Fusion™ SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL95712 controller supports two
Voltage Regulators (VRs) for Core and Northbridge outputs. The
Core VR can be configured for 4-, 3-, 2-, or 1-phase operation while
the Northbridge VR supports 3-, 2- or 1-phase configurations for
maximum flexibility. The two VRs share a serial control bus to
communicate with the AMD CPU and achieve lower cost and
smaller board area compared with two-chip solutions.
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3™ Technology. Compared to traditional modulators,
the R3™ modulator can automatically change switching
frequency for faster transient settling time during load transients
and improved light load efficiency.
The ISL95712 has several other key features. Both outputs
support DCR current sensing with a single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. They also utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good indicators.
FN8566
Rev 1.00
November 2, 2015
Features
• Supports AMD SVI 2.0 serial data bus interface and PMBus
- Serial VID clock frequency range 100kHz to 25MHz
• Dual output controller with 12V integrated core gate drivers
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2-, 3- or 4-phase for the core output and
1- , 2- or 3-phase for the Northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current and voltage telemetry
• Differential remote voltage sensing
• High efficiency across entire load range
• Programmable slew rate
• Programmable VID offset and droop on both outputs
• Programmable switching frequency for both outputs
• Excellent dynamic current balance between phases
• Protection: OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 52 Ld 6x6 QFN package
- Pb-free (RoHS compliant)
Applications
• AMD Fusion CPU/GPU core power
• Desktop computers
Performance
100
90
80
EFFICIENCY (%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
DAC = 1.500V
90
100
110
LOAD CURRENT (A)
CORE
(PSI1)
NORTHBRIDGE
OUTPUT VOLTAGE (V)
CORE
1.5
CORE
1.4
1.3
NORTHBRIDGE
1.2
1.1
DAC = 1.500V
1.0
0
10
20
30
40
50
60
70
80
90
100
110
1.6
LOAD CURRENT (A)
FIGURE 1. EFFICIENCY vs LOAD
FIGURE 2. V
OUT
vs LOAD
FN8566 Rev 1.00
November 2, 2015
Page 1 of 35
ISL95712
Table of Contents
Simplified Application Circuit for High Power CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Diode Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current-Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal Monitor [NTC, NTC_NB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FN8566 Rev 1.00
November 2, 2015
Page 2 of 35
ISL95712
Simplified Application Circuit for High Power CPU Core
ENABLE
VDDP
VDD
NB_PH1
NB_PH2
VNB1
VNB2
NB_PH1
NB_PH2
COMP_NB
Cn
Ri
ISUMN_NB
NTC
ISUMP_NB
PROG
+12V
ISEN1_NB
ISEN2_NB
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
NB_PH1
VNB1
VNB
+12V
*OPTIONAL
VNB_SENSE
VSEN_NB
IMON_NB
NTC_NB
I2DATA
I2CLK
PWM2_NB
ISL6625A
*
*
FB_NB
NB_PH2
VNB2
+12V
THERMAL INDICATOR
VR_HOT_L
PWROK
SVT
PWM4
ISL6625A
µP
SVD
SVC
VDDIO
IMON
NTC
PWM3
COMP
ISL6625A
PH4
VO4
+12V
ISL95712
PH3
VO3
*
*
FB
BOOT2
VSEN
RTN
ISEN1
ISEN2
ISEN3
ISEN4
Ri
BOOT1
UGATE1
PGOOD_NB
GND PAD
PGOOD
PHASE1
LGATE1
PH1
VO1
+12V
LGATE2
PH2
VO2
UGATE2
PHASE2
VCORE
+12V
*OPTIONAL
VCORE_SENSE
PH1
PH2
PH3
PH4
VO1
VO2
VO3
VO4
Cn
NTC
ISUMN
ISUMP
PH1
PH2
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
FN8566 Rev 1.00
November 2, 2015
PH3
PH4
Page 3 of 35
ISL95712
Pin Configuration
ISL95712
(52 LD QFN)
TOP VIEW
PGOOD_NB
ISUMN_NB
ISUMP_NB
PWM3_NB
PWM2_NB
COMP_NB
ISEN2_NB
ISEN1_NB
VSEN_NB
FB_NB
52 51 50 49 48 47 46 45 44 43 42 41 40
ISEN3_NB
NTC_NB
IMON_NB
PROG
I2DATA
I2CLK
1
2
3
4
5
6
7
8
9
GND
(BOTTOM PAD)
39
PWM4
38 PWM3
37 BOOT1_NB
36 UGATE1_NB
35 PHASE1_NB
34 LGATE1_NB
33 LGATE2
32 VDDP
31 UGATE2
30 PHASE2
29 BOOT2
28 LGATE1
27 UGATE1
14 15 16 17 18 19 20 21 22 23 24 25 26
PGOOD
COMP
BOOT1
PHASE1
ISEN3
ISUMP
ISUMN
IISEN2
ISEN1
VSEN
RTN
FB
VDD
SVC
VR_HOT_L
SVD
VDDIO
SVT
ENABLE
PWROK 10
IMON 11
NTC
12
ISEN4
13
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
SYMBOL
ISEN3_NB
NTC_NB
IMON_NB
SVC
VR_HOT_L
SVD
VDDIO
SVT
ENABLE
PWROK
DESCRIPTION
Individual current sensing for Channel 3 of the Northbridge VR. When ISEN3_NB is pulled to +5V, the
controller will disable Channel 3 and the Northbridge VR will run 2-phase.
Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.
Northbridge output current monitor. A current proportional to the Northbridge VR output current is
sourced from this pin.
Serial VID clock input from the CPU processor master device.
Thermal indicator signal to AMD CPU. Thermal overload open-drain output indicator active LOW.
Serial VID data bidirectional signal from the CPU processor master device to the VR.
VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller
IC for this processor I/O signal level.
Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly
complete signal provided from this pin.
Enable input. A high level logic on this pin enables both VRs.
System power-good input. When this pin is high, the SVI 2 interface is active and the I
2
C protocol is
running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This
pin must be low prior to the ISL95712 PGOOD output going high per the AMD SVI 2.0 Controller
Guidelines.
Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.
Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.
ISEN4 is the individual current sensing for Channel 4 of the Core VR. When ISEN4 is pulled to +5V, the
controller disables Channel 4, and the Core VR runs in three-phase mode.
11
12
13
IMON
NTC
ISEN4
FN8566 Rev 1.00
November 2, 2015
Page 4 of 35
ISL95712
Pin Descriptions
(Continued)
PIN NUMBER
14
15
16
SYMBOL
ISEN3
ISEN2
ISEN1
DESCRIPTION
ISEN3 is the individual current sensing for Channel 3 of the Core VR. When ISEN3 is pulled to +5V, the
controller disables Channel 3, and the Core VR runs in two-phase mode.
Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller
disables Channel 2, and the Core VR runs in single-phase mode.
Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left
open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is
shut down.
Noninverting input of the transconductance amplifier for current monitor and load line of Core output.
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the
microprocessor die.
Output voltage feedback to the inverting input of the Core controller error amplifier.
5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high
quality, X7R dielectric MLCC capacitor is recommended.
Open-drain output to indicate the Core output is ready to supply regulated voltage. Pull-up externally to
VDD or 3.3V through a resistor.
Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.
Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot capacitor is charged, through
an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of
Phase 1.
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate
of the Phase 1 high-side MOSFET(s).
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate
of the Phase 1 low-side MOSFET(s).
Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through
an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output
inductor of Phase 2.
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate
of the Phase 2 high-side MOSFET(s).
Input voltage bias for the internal gate drivers. Connect +12V to the VDDP pin. Decouple with at least 1µF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate
of the Phase 2 low-side MOSFET(s).
Output of Northbridge Phase 1 low-side MOSFET gate driver. Connect the LGATE1_NB pin to the gate of
the Northbridge VR Phase 1 low-side MOSFET(s).
Current return path for Northbridge VR Phase 1 high-side MOSFET gate driver. Connect the PHASE1_NB
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output
inductor of Northbridge Phase 1.
Output of the Phase 1 high-side MOSFET gate driver of the Northbridge VR. Connect the UGATE1_NB pin
to the gate of the Northbridge VR Phase 1 high-side MOSFET(s).
17
18
19
20
21
22
23
24
25
ISUMP
ISUMN
VSEN
RTN
FB
VDD
PGOOD
COMP
BOOT1
26
PHASE1
27
28
29
UGATE1
LGATE1
BOOT2
30
PHASE2
31
32
33
34
35
UGATE2
VDDP
LGATE2
LGATE1_NB
PHASE1_NB
36
UGATE1_NB
FN8566 Rev 1.00
November 2, 2015
Page 5 of 35
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