TECHNICAL NOTE
Large Current External FET Controller Type Switching Regulator
Step-down,
High-efficiency
Switching Regulators
(Controller type)
BD9011EKN , BD9011KV , BD9775FV
■
BD9011EKN, BD9011KV
●Overview
The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency.
It supports a wide input range, enabling low power consumption ecodesign for an array of electronics.
●Features
1) Wide input voltage range: 3.9V to 30V
2) Precision voltage references: 0.8V±1%
3) FET direct drive
4) Rectification switching for increased efficiency
5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz)
6) Built-in selected OFF latch and auto remove over current protection
7) Built-in independent power up/power down sequencing control
8) Make various application , step-down , step-up and step-up-down
9) Small footprint packages: HQFN36V, VQFP48C
●Applications
Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players,
etc.
●Absolute
Maximum Ratings (Ta=25℃)
Parameter
EXTVCC Voltage
VCCCL1,2 Voltage
CL1,2 Voltage
SW1,2 Voltage
BOOT1,2 Voltage
BOOT1,2-SW1,2
Voltage
STB, EN1,2 Voltage
VREG5,5A
VREG33
SS1,2½FB1,2
Symbol
EXTVCC
VCCCL1,2
CL1,2
SW1,2
BOOT1,2
BOOT1,2-SW1,2
STB, EN1,2
VREG5,5A
VREG33
SS1,2½FB1,2
Rating
34
34
*1
*1
Unit
V
V
V
V
V
Parameter
COMP1,2 Voltage
DET1,2 Voltage
RT½SYNC Voltage
Symbol
COMP1,2
DET1,2
RT½SYNC
Rating
Unit
VREG5
V
34
34
40
7
*1
*1
0.875
（HQFN36V）
Power Dissipation
Pd
1.1
（VQFP48C）
*2
*2
W
*1
V
V
V
V
V
W
VCC
7
VREG5
VREG5
Operating
temperature
Storage temperature
Junction temperature
Topr
Tstg
Tj
-40 to +105
-55 to +150
+150
℃
℃
℃
*1 Regardless of the listed rating, do not exceed Pd in any circumstances.
*2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/℃（
HQFN36V） or 8.8
mW/℃（V
QFP48C）
above 25℃.
Sep. 2008
●Operating
conditions (Ta=25℃)
Parameter
Input voltage 1
Input voltage 2
BOOT－SW voltage
Carrier frequency
Synchronous frequency
Synchronous pulse duty
Min OFF pulse
*1 After more than 4.5V, voltage range.
*2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.
Symbol
EXTVCC
VCC
BOOT－SW
OSC
SYNC
Duty
TMIN
Min.
3.9
*1 *2
3.9
*1 *2
4.5
250
OSC
40
-
Typ.
12
12
5
300
-
50
100
Max.
30
30
VREG5
550
550
60
-
Unit
V
V
V
kHz
kHz
％
nsec
★This
product is not designed to provide resistance against radiation.
●Electrical
characteristics (Unless otherwise specified, Ta=25℃
VCC=12V STB=5V EN1,2=5V
)
Parameter
VIN bias current
Shutdown mode current
［Error
Amp Block½
Feedback reference voltage
Feedback reference voltage
(Ta=-40 to 105℃)
Open circuit voltage gain
VO input bias current
［FET
Driver Block½
HG high side ON resistance
HG low side ON resistance
LG high side ON resistance
LG low side ON resistance
［Oscillator½
Carrier frequency
Synchronous frequency
［Over
Current Protection Block½
CL threshold voltage
CL threshold voltage
（Ta=-40
to 105℃）
［VREG
Block½
VREG5 output voltage
VREG33 reference voltage
VREG5 threshold voltage
VREG5 hysteresis voltage
［Soft
start block½
Charge current
ISS
6.5
10
13.5
14
μA
μA
VSS=1V
VSS=1V,Ta=-40 to 105℃
※
VREG5
VREG33
VREG_UVLO
DVREG_UVLO
4.8
3.0
2.6
50
5
3.3
2.8
100
5.2
3.6
3.0
200
V
V
V
mV
IREF=6mA
IREG=6mA
VREG:Sweep down
VREG:Sweep up
Vswth
Vswth+
70
67
90
90
110
113
½V
½V
Ta=-40 to 105℃
※
FOSC
Fsync
270
-
300
500
330
-
kHz
kHz
RT=100 kΩ
RT=100 kΩ,SYNC=500kHz
HGhon
HGlon
LGhon
LGlon
-
-
-
-
1.5
1.0
1.5
0.5
-
-
-
-
Ω
Ω
Ω
Ω
VOB
VOB+
Averr
IVo+
0.792
0.784
-
-
0.800
0.800
46
-
0.808
0.816
-
1
V
V
dB
μA
Ta=-40 to 105℃
※
Symbol
IIN
IST
Limit
Min.
-
-
Typ.
5
0
Max.
10
10
Unit
mA
μA
VSTB=0V
Conditions
Charge current
ISS+
6
10
(Ta=-40 to 105℃)
Note: Not all shipped products are subject to outgoing inspection.
2/29
●Reference
data (Unless otherwise specified, Ta=25℃)
100
90
80
EFFICIENCY[%]
70
60
50
40
30
20
10
0
0
2.6V
3.3V
5.0V
100
90
3.3V
CIRCUIT CURRENT[mA]
80
EFFICIENCY[%]
6
5
1.8V
1.2V
70
60
50
40
30
20
5.0V
4
3
2
1
0
105℃
25℃
-40℃
VIN=12V
1
2
OUTPUT CURRENT：Io[A]
3
10
0
6
9
Io=2A
12
15
18
21
INPUT VOLTAGE ： V
IN
[V]
24
0
10
20
INPUT VOLTAGE：V
IN
[V]
30
Fig.1 Efficiency 1
Fig.2 Efficiency 2
Fig.3 Circuit current
0.816
REFERENCE VOLTAGE ： VOB[V]
過電流検出電圧 ： Vswth[mV]
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.784
-40 -15
10
35
60
85 110
AMBIENT TEMPERATURE ： Ta[℃]
110
OSILATING FREQUENCY ： F [kHz]
OSC
330
320
310
300
290
280
270
RT=100kΩ
100
90
80
70
60
-40
-15
10
35
60
85
110
AMBIENT TEMPERATURE ： Ta[℃]
-40
-15
10
35
60
85
110
AMBIENT TEMPERATURE ： Ta[℃]
Fig.4 Reference voltage vs.
temperature characteristics
5.25
5.00
OUT PUT VOLTAGE ： Vo[V]
Fig.5 Over current detection vs.
temperature characteristics
6
5
OUT PUT VOLTAGE ： Vo[V]
3.0
2.5
Fig.6 Frequency vs.
temperature characteristics
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
-40
-15
10
OUT PUT VOLTAGE ： Vo[V]
VREG5
5.0V
4
3
R
CL
=15mΩ
2.0
1.5
3.3V
2
1
0
0
5
10
15
20
INPUT VOLTAGE ： V
IN
[V]
25
LOFF=H
1.0
VREG33
LOFF=L
0.5
0.0
0
1
2
3
4
5
6
OUTPUT CURRENT: Io[A]
35
60
85
110
AMBIENT TEMPERATURE ： Ta[℃]
Fig.7 Internal Reg vs.
temperature characteristics
6
Fig.8 Line regulation
Fig.9 Load regulation
OUTPU T VOLTAGE ： Vo[V]
5
50mV/div
V
OUT
V
OUT
50mV/div
4
105℃
3
25℃
2
1
0
0
2
4
INPUT VOLTAGE：V
EN
[V]
6
-40℃
I
OUT
1A/div
I
OUT
1A/div
Fig.10 EN threshold voltage
Fig.11 Load transient response 1
Fig.12 Load transient response 2
3/29
●Block
diagram
(Parentheses indicate VQFP48C pin numbers)
EXTVCC
22
(41)
5V Reg
STB VCC
10
(25)
32
(7)
RT
15
(33)
SYNC
16
(34)
3.3V Reg
VREG5
24(44)
B.G
SYNC
5(19)
VREG33
LLM
VCCCL1
CL1
BOOT1
OUTH1
SW1
VREG5A
OUTL1
DGND1
FB1
SS1
COMP1
17(35)
UVLO
TSD
2.7V
TSD
OSC
33(8)
34(10)
VCCCL2
CL2
BOOT2
OUTH2
SW2
OUTL2
DGND2
FB2
SS2
COMP2
31(5)
30(3)
29(2)
28(1)
27(48)
OCP
Set
DRV
Reset
Set
Reset
DRV
OCP
35(11)
36(12)
SW
VREG5
SW
TSD
UVLO
Q
Reset Set
PW M
COMP
TSD
UVLO
1(13)
4(17)
3(15)
2(14)
LOGIC
LOGIC
25(46)
26(47)
21(39)
19(37)
20(38)
－
＋
＋
0.8V
Err Amp
Slope
Slope
PW M
COMP
Q
Set Reset
Err Amp
6(21)
8(23)
0.8V
UVLO
Ｏ
7(22)
Q
Reset
Sequence DET
Set
Q
Reset
Sequence DET
0.56V
0.56V
Set
18
(36)
14
(31)
12
(27)
11
(26)
(30)
13
(29)
9
(24)
DET2
LOFF
EN2
EN1 (GNDS) GND
DET1
Fig-13
●Pin
configuration
BD9011EKN（HQFN36V）
EXTVCC
●
PIN function table
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin name
SW1
DGND1
OUTL1
VREG5A
VREG33
FB1
COMP1
SS1
DET1
STB
EN1
EN2
GND
LOFF
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
EXTVCC
－
VREG5
OUTL2
DGND2
SW2
OUTH2
BOOT2
CL2
VCCCL2
VCC
VCCCL1
CL1
BOOT1
OUTH1
Function
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
FET drive REG input
Reference input REG output
Error amp input 1
Error amp output 1
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1ON/OFF pin
Output 2ON/OFFpin
Ground
Over current protection OFF latch
function ON/OFF pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
External power input pin
N.C.
FET drive REG output
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
Hi side FET gate drive pin 2
OUTH2 driver power pin
Over current detector setting pin 2
Over current detection VCC2
Input power pin
Over current detection VCC1
Over current detector setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
COMP2
20
DGND2
VREG5
OUTL2
SW2
27
26
25
24
23
22
21
19
18
DET2
17
LMM
16
SYNC
15
RT
14
LOFF
13
GND
12
EN2
11
EN1
10
STB
OUTH2
28
BOOT2
29
CL2
30
VCCCL2
31
VCC
32
VCCCL1
33
CL1
34
BOOT1
35
OUTH1
36
1
2
3
4
5
6
7
8
9
COMP1
FB1
OUTL1
SW1
VREG33
DGND1
SS1
VREG5A
Fig-14
DET1
SS2
FB2
4/29
●Pin
configuration
BD9011KV（VQFP48C）
GNDS
SYNC
●
Pin function table
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
OUTH2
BOOT2
CL2
N.C
VCCCL2
N.C
VCC
VCCCL1
N.C
CL1
BOOT1
OUTH1
SW1
DGND1
OUTL1
N.C
VREG5A
N.C
VREG33
N.C
FB1
COMP1
SS1
DET1
STB
EN1
EN2
N.C
GND
GNDS
LOFF
N.C
RT
SYNC
LLM
DET2
SS2
COMP2
FB2
N.C
EXTVCC
N.C
N.C
VREG5
N.C
OUTL2
DGND2
SW2
Function
High side FET gate drive pin 2
OUTH2 driver power pin
Over current detection pin 2
Non-connect (unused) pin
Over current detection VCC2
Non-connect (unused) pin
Input power pin
Over current detection CC1
Non-connect (unused) pin
Over current detection setting pin 1
OUTH1 driver power pin
High side FET gate drive pin 1
High side FET source pin 1
Low side FET source pin 1
Low side FET gate drive pin 1
Non-connect (unused) pin
FET drive REG input
Non-connect (unused) pin
Reference input REG output
Non-connect (unused) pin
Error amp input 1
Error amp output 1
Soft start setting pin 1
FB detector output 1
Standby ON/OFF pin
Output 1 ON/OFF pin
Output 2 ON/OFF pin
Non-connect (unused) pin
Ground
Sense ground
Over current protection OFF latch
function ON/OFF pin
Non-connect (unused) pin
Switching frequency setting pin
External synchronous pulse input pin
Built-in pull-down resistor pin
FB detector output 2
Soft start setting pin 2
Error amp output 2
Error amp input 2
Non-connect (unused) pin
External power input pin
Non-connect (unused) pin
Non-connect (unused) pin
FET drive REG output
Non-connect (unused) pin
Low side FET gate drive pin 2
Low side FET source pin 2
High side FET source pin 2
LOFF
DET2
GND
36
35
34
33
32
31
30
29
28
27
26
EN1
25
24
DET1
23
SS1
22
COMP1
21
FB1
20
N.C
19
VREG33
18
N.C
17
VREG5A
16
N.C
15
OUTL1
14
DGND1
13
SW1
SS2
37
COMP2
38
FB2
39
N.C
40
EXTVCC
41
N.C
42
N.C
43
VREG5
44
N.C
45
OUTL2
46
DGND2
47
SW2
48
1
2
3
4
5
6
7
8
9
10
11
12
BOOT2
BOOT1
N.C
OUTH2
VCCCL2
Fig-15
●Block
functional descriptions
・Error
amp
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is
used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.
・Oscillator
(OSC)
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.
・
SLOPE
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.
・PWM
COMP
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the
SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.
・Reference
voltage (5Vreg，33Vreg)
This block generates the internal reference voltages: 5V and 3.3V.
・External
synchronization (SYNC)
Determines the switching frequency, based on the external pulse applied.
・Over
current protection (OCP)
Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,
and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch
mode ends when the latch is set to STB, EN.
・Sequence
control (Sequence DET)
Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.
・Protection
circuits (UVLO/TSD)
The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when temperature falls back below the threshold value.
VCCCL1
OUTH1
VCC
N.C
N.C
CL2
CL1
STB
LLM
EN2
N.C
N.C
RT
5/29
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