FemtoClock
®
NG Dual Universal
Frequency Translator
DATASHEET
General Description
The IDT8T49N244I is a dual PLL using FemtoClock
®
NG
technology. It integrates low phase noise Frequency Translation /
Synthesis and Jitter attenuation. It includes alarm and monitoring
functions suitable for networking and communications applications.
The device has two fully independent PLLs. Each PLL is able to
generate any output frequency in the 0.98MHz - 312.5MHz range
and most output frequencies in the 312.5MHz - 1,300MHz range
(see Table 3 for details). A wide range of input reference clocks may
be used as the source for the output frequencies.
Each PLL of IDT8T49N244I has three operating modes to support a
very broad spectrum of applications:
1) Frequency Synthesizer
IDT8T49N244I
Features
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Fourth generation FemtoClock
®
NG technology
Two fully independent PLLs
Universal Frequency Translator
TM
/Frequency Synthesizer and
Jitter attenuator
Outputs are programmable as LVPECL or LVDS
•
Programmable output frequency: 0.98MHz up to 1,300MHz
Two differential inputs per PLL support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz (Low-Bandwidth mode)
Input frequency range: 16MHz - 710MHz (High-Bandwidth mode)
REFCLK frequency range: 16MHz - 40MHz
Input clock monitor on each PLL will smoothly switch between
redundant input references
Factory-set register configuration for power-up default state
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Synthesizes output frequencies from an external reference
clock REFCLK.
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
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Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 161.1328125MHz, using a 40MHz REFCLK
(12kHz - 20MHz): 486fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz, using a 40MHz REFCLK
(12kHz - 20MHz): 326fs (typical), Synthesizer Mode (Integer FB)
Supply modes:
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V (LVPECL only)
2.5V / 2.5V / 2.5V
-40°C to 85°C ambient operating temperature
10mm X 10mm CABGA package
Lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
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Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured.
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IDT8T49N244AASGI REVISION A JUNE 28, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T49N244I Data Sheet
FemtoClock
®
NG Dual Universal Frequency Translator™
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
E5
G8, G7
F8,
F7
H3, G3
H4,
G4
J9, J8
H6, J4
J1, H1
F2, D1
J6, J5
F1, E1
H7
G2
E8
H5
Name
REFCLK
CLK0A,
CLK1A
nCLK0A,
nCLK1A
CLK0B,
CLK1B
nCLK0B,
nCLK1B
Q0A, nQ0A
Q1A, nQ1A
Q0B, nQ0B
Q1B, nQ1B
LF0A, LF1A
LF0B, LF1B
Rsvd
Rsvd
LOCKA
LOCKB
Input
Input
Input
Input
Input
Output
Output
Output
Output
Analog I/O
Analog I/O
Input
Input
Output
Output
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Reference clock for device operation.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
2 default when left floating (set by the
internal pullup and pulldown resistors).
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Loop filter connection node pins. LF0A is the output, LF1A is the input.
Loop filter connection node pins. LF0B is the output, LF1B is the input.
Reserved, connect to V
EE
Reserved, connect to V
EE
Lock Indicator - indicates that PLLA is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that PLLB is in a locked condition.
LVCMOS/LVTTL interface levels.
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0A, nCLK0A (default)
1 = CLK1A, nCLK1A
Input clock select. Selects the active differential clock input.
0 = CLK0B, nCLK0B (default)
1 = CLK1B, nCLK1B
Bypasses the VCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
I
2
C Data Input/Output. Open drain.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Analog power supply for PLLA.
Output power supply for PLLA.
Core power supply for PLLA.
Analog power supply for PLLB.
Output power supply for PLLB.
3
©2013 Integrated Device Technology, Inc.
F6
CLK_SELA
Input
F4
CLK_SELB
Input
Pulldown
E6
G6
G5
E7
G9
F5
E3
J3
PLL_BYPAS
S
SDATA
SCLK
V
CCA_A
V
CCO_A
V
CC_A
V
CCA_B
V
CCO_B
Input
I/O
Input
Power
Power
Power
Power
Power
Pulldown
Pullup
Pullup
IDT8T49N244AASGI REVISION A JUNE 28, 2013
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