PSMN1R4-40YLD
30 November 2017
N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in
LFPAK56 using NextPower-S3 technology
Product data sheet
1. General description
240 Amp, logic level gate drive N-channel enhancement mode MOSFET in 175 °C LFPAK56
package using advanced TrenchMOS Superjunction technology. This product has been designed
and qualified for high performance power switching applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
240 A capability
Avalanche rated, 100% tested at I
AS
= 190 A
NextPower-S3 technology delivers 'superfast switching with soft recovery'
Low Q
RR
, Q
G
and Q
GD
for high system efficiency and low EMI designs
Schottky-Plus body-diode, gives soft switching without the associated high I
DSS
leakage
Optimised for 4.5 V gate drive utilising NextPower-S3 Superjunction technology
High reliability LFPAK (Power SO8) package, copper-clip, solder die attach and
qualified to 175 °C
Exposed leads can be wave soldered, visual solder joint inspection and high quality solder
joints
Low parasitic inductance and resistance
3. Applications
•
•
•
•
•
Synchronous rectification
DC-to-DC converters
High performance & high efficiency server power supply
Motor control
Power OR-ing
4. Quick reference data
Table 1. Quick reference data
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 10
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 10
Conditions
25 °C ≤ T
j
≤ 175 °C
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
[1]
Min
-
-
-
-55
-
-
Typ
-
-
-
-
1.38
1.12
Max
40
240
238
175
1.85
1.4
Unit
V
A
W
°C
mΩ
mΩ
Static characteristics
Nexperia
PSMN1R4-40YLD
N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology
Symbol
Q
GD
Q
G(tot)
[1]
Parameter
gate-drain charge
total gate charge
Conditions
I
D
= 25 A; V
DS
= 20 V; V
GS
= 4.5 V;
Fig. 12; Fig. 13
Min
-
-
Typ
13
45
Max
-
-
Unit
nC
nC
Dynamic characteristics
240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,
thermal design and operating temperature.
5. Pinning information
Table 2. Pinning information
Pin
1
2
3
4
mb
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1 2 3 4
Simplified outline
mb
Graphic symbol
D
G
mbb076
S
LFPAK56; Power-
SO8 (SOT669)
6. Ordering information
Table 3. Ordering information
Type number
PSMN1R4-40YLD
Package
Name
LFPAK56;
Power-SO8
Description
Plastic single-ended surface-mounted package (LFPAK56;
Power-SO8); 4 leads
Version
SOT669
7. Marking
Table 4. Marking codes
Type number
PSMN1R4-40YLD
Marking code
1D440L
PSMN1R4-40YLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
30 November 2017
2 / 15
Nexperia
PSMN1R4-40YLD
N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DSM
V
DGR
V
GS
P
tot
I
D
I
DM
T
stg
T
j
T
sld(M)
V
ESD
Parameter
drain-source voltage
peak drain-source
voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
peak drain current
storage temperature
junction temperature
peak soldering
temperature
electrostatic discharge
voltage
source current
peak source current
non-repetitive drain-
source avalanche
energy
HBM
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 2
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
[1]
Conditions
25 °C ≤ T
j
≤ 175 °C
t
p
≤ 20 ns; f ≤ 500 kHz; E
DS(AL)
≤ 200 nJ;
pulsed
25 °C ≤ T
j
≤ 175 °C; R
GS
= 20 kΩ
Min
-
-
-
-20
-
-
-
-
-55
-55
-
2
Max
40
45
40
20
238
240
214
1201
175
175
260
-
Unit
V
V
V
V
W
A
A
A
°C
°C
°C
kV
Source-drain diode
I
S
I
SM
E
DS(AL)S
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 74 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
t
p
= 0.23 ms
I
D
= 25 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
t
p
= 2.52 ms
I
AS
[1]
[2]
-
-
[2]
-
198.6
1201
446
A
A
mJ
Avalanche ruggedness
[2]
-
1641
mJ
non-repetitive avalanche V
sup
≤ 40 V; V
GS
= 10 V; T
j(init)
= 25 °C;
current
R
GS
= 50 Ω
[2]
-
190
A
240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB,
thermal design and operating temperature.
Protected by 100% test
PSMN1R4-40YLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
30 November 2017
3 / 15
Nexperia
PSMN1R4-40YLD
N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology
120
P
der
(%)
80
03aa16
I
D
(A)
320
aaa-013028
240
(1)
160
40
80
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
(1) 240A Continuous current has been successfully
demonstrate during application tests. Practically
the current will be limited by PCB, thermal design
and operation temperature.
V
GS
≥ 10 V
Continuous drain current as a function of
mounting base temperature
aaa-013030
I
D
(A)
10
4
10
3
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 µs
100 µs
10
2
10
DC
1 ms
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN1R4-40YLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
30 November 2017
4 / 15
Nexperia
PSMN1R4-40YLD
N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
R
th(j-mb)
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
1
δ = 0.5
0.2
0.1
0.05
0.02
10
-2
single shot
t
p
T
Conditions
Fig. 4
Min
-
Typ
0.56
Max
0.63
Unit
K/W
R
th(j-a)
Fig. 5
Fig. 6
-
-
50
125
-
-
aaa-009500
K/W
K/W
Z
th(j-mb)
(K/W)
10
-1
P
δ=
t
p
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-005750
aaa-005751
Fig. 5.
PCB layout for thermal resistance junction to
ambient 1” square pad; FR4 Board; 2oz copper
Fig. 6.
PCB layout for thermal resistance junction to
ambient minimum footprint;FR4 board; 2oz
copper
PSMN1R4-40YLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
30 November 2017
5 / 15
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