74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
Rev. 5 — 7 November 2011
Product data sheet
1. General description
The 74ABT821 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT821 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data/address paths of
buses carrying parity.
The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.
The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers.
The device is controlled by the clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active LOW output enable (OE) controls all ten 3-state buffers independent of the
register operation. When OE is LOW, the data in the register appears at the outputs.
When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features and benefits
High-speed parallel registers with positive-edge triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and
32
mA
Power-on 3-state
Power-on reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT821D
74ABT821DB
74ABT821PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
4. Functional diagram
1
13
EN
C2
23
22
21
20
19
18
17
16
15
14
001aac735
2
3
4
5
6
7
8
9
10 11
2
3
2D
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
1
CP
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
001aac734
4
5
6
7
8
9
10
11
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D
D
D
D
D
D
D
D
D
D
CP Q
CP
13
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
OE
1
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
001aac736
Fig 3. Logic diagram
74ABT821
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
2 of 16
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
74ABT821
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 CP
001aac733
D8 10
D9 11
GND 12
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
OE
D0 to D9
GND
CP
Q0 to Q9
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12
13
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
24
Description
output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
data output
supply voltage
74ABT821
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
3 of 16
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
6. Functional description
6.1 Function table
Table 3.
Input
OE
L
L
L
H
H
[1]
Function table
[1]
Internal register
CP
NC
NC
D0 to D9
l
h
X
X
Dn
L
H
NC
NC
Dn
Output
Q0 to Q9
L
H
NC
Z
Z
load and read
register
hold
disable outputs
Operating mode
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
74ABT821
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
4 of 16
NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
64
5
+85
Unit
V
V
V
V
mA
mA
ns/V
C
74ABT821
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
5 of 16
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