NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
USB Interface
USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
MainFlash
to 512 Kbyte
Built-in Flash Accelerator System with 16 Kbyte trace
buffer memory
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
Up
USB device
Full-Speed supported
Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
• EndPoint 3 to 5 can be selected Bulk-transfer or
Interrupt-transfer
• EndPoint 1 to 5 is comprised Double Buffer
• The size of each EndPoint is as follows.
• EndPoint 0, 2 to 5: 64 bytes
• EndPoint 1: 256 bytes
USB2.0
WorkFlash
32
Kbyte
Read cycle
4 wait-cycle: the operation frequency more than 72 MHz
2 wait-cycle: the operation frequency more than 40 MHz,
and to 72 MHz
0 wait-cycle: the operation frequency to 40 MHz
Security function is shared with code protection
USB host
USB2.0
[SRAM]
This Series contain a total of up to 64 Kbyte on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0:
SRAM1:
Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
Up to 32 Kbyte
Up to 32 Kbyte
Cypress Semiconductor Corporation
Document Number: 002-05619 Rev.*C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 21, 2017
MB9B310R Series
Multi-function Serial Interface (Max eight channels)
4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7),
4 channels without FIFO (ch.0 to ch.3)
A/D Converter (Max 16 channels)
12-bit A/D Converter
Successive Approximation
Built-in
Register type
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
3 unit
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
UART
Full-duplex
double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
CSIO
Full-duplex
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set
which I/O port the peripheral function can be allocated.
double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
LIN
protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit
length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
LIN
I
2
C
Standard-mode
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 103 fast general purpose I/O Ports @ 120 pin Package
Some pin is 5 V tolerant I/O.
See "4 List of Pin Functions" to confirm the corresponding
pins.
(Max 100 kbps) / Fast-mode (Max 400
kbps) supported
Multi-function Timer (Max three units)
DMA Controller (Eight channels)
DMA Controller has an independent bus for CPU, so CPU
and DMA Controller can process simultaneously.
The Multi-function timer is composed of the following blocks.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activating compare × 3 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Document Number: 002-05619 Rev.*C
Page 2 of 117
MB9B310R Series
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in
any power consumption mode except Stop mode.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
Quadrature Position/Revolution Counter (QPRC)
(Max three channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it
is possible to use up/down counter.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
Clocks
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit
down counters.
Operation mode is selectable from the followings for each
channel.
Clock:
Sub Clock:
High-speed internal CR Clock:
Low-speed internal CR Clock:
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
Resets
Reset
Free-running
Periodic (=Reload)
One-shot
requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Watch Counter
The Watch counter is used for wake up from power
consumption mode.
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
External Interrupt Controller Unit
Up to 16 external interrupt input pin
Include one non-maskable interrupt (NMI)
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05619 Rev.*C
Page 3 of 117
MB9B310R Series
Low-Power Consumption Mode
Three power consumption modes supported.
Power Supply
Two Power Supplies
range voltage:
VCC
= 2.7 V to 5.5 V
USB for USB I/O voltage:
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Wide
Sleep
Timer
Stop
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Document Number: 002-05619 Rev.*C
Page 4 of 117
MB9B310R Series
Table of Contents
Features .............................................................................................................................................................................. 1
List of Pin Functions ................................................................................................................................................. 14
5.
I/O Circuit Type .......................................................................................................................................................... 41
Precautions for Product Design ................................................................................................................................ 46
6.2
Precautions for Package Mounting ........................................................................................................................... 47
6.3
Precautions for Use Environment ............................................................................................................................. 49
Pin Status in Each CPU State ................................................................................................................................... 57
Absolute Maximum Ratings ...................................................................................................................................... 61
DC Characteristics .................................................................................................................................................... 64
12.3.1
Current Rating ....................................................................................................................................................... 64
AC Characteristics .................................................................................................................................................... 68
12.4.1
Main Clock Input Characteristics ........................................................................................................................... 68
12.4.2
Sub Clock Input Characteristics ............................................................................................................................. 69
External Bus Timing ............................................................................................................................................... 72
12.4.9
Base Timer Input Timing ........................................................................................................................................ 81
C Timing .............................................................................................................................................................. 93
USB Characteristics.................................................................................................................................................. 99
Write / Erase time ................................................................................................................................................ 104
12.8.2
Erase/write cycles and data hold time.................................................................................................................. 104
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