SPT9689
DUAL ULTRAFAST VOLTAGE COMPARATOR
TECHNICAL DATA
FEBRUARY 20, 2001
FEATURES
•
•
•
•
•
•
650 ps propagation delay
100 ps propagation delay variation
70 dB CMRR
Low feedthrough and crosstalk
Differential latch control
ECL compatible
APPLICATIONS
•
•
•
•
•
•
•
•
Automated test equipment
High-speed instrumentation
Window comparators
High-speed timing
Line receivers
High-speed triggers
Threshold detection
Peak detection
GENERAL DESCRIPTION
The SPT9689 is a
Subnanosecond
monolithic dual com-
parator. The propagation delay variation is less than
100 ps from 5 to 50 mV input overdrive voltage. The input
slew rate is 10 V/ns. The device utilizes a high precision
differential input stage with a common-mode range of
–2.5 V to +4.0 V.
ECL-compatible complementary digital outputs are ca-
pable of driving 50
Ω
terminated transmission lines and
providing 30 mA output drive. The SPT9689 is pin compat-
ible with the SPT9687. It is available in 20-lead PLCC and
20-contact LCC packages over the industrial temperature
range. The SPT9689 is also available in die form.
BLOCK DIAGRAM
INVERTING
INPUT
LATCH ENABLE
NONINVERTING
INPUT
A
+
LATCH ENABLE
Q OUTPUT
Q OUTPUT
V
EE
V
CC
GND
B
GND
A
Q OUTPUT
Q OUTPUT
LATCH ENABLE
B
+
LATCH ENABLE
NONINVERTING
INPUT
INVERTING
INPUT
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
Positive Supply Voltage (V
CC
to GND) .... –0.5 to +6.0 V
Negative Supply Voltage (V
EE
to GND) .. –6.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Input Voltages
Input Common Mode Voltage ................. –4.0 to +5.0 V
Differential Input Voltage ........................ –3.0 to +3.0 V
Input Voltage, Latch Controls .................... V
EE
to 0.5 V
Output
Output Current ................................................... 30 mA
Temperature
Operating Temperature, ambient ............ –40 to +85 °C
junction ..................... +150 °C
Lead Temperature, (soldering 60 seconds) ..... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= +25 °C, V
CC
= +5.0 V, V
EE
=–5.20 V, R
L
= 50 Ohm to –2 V, unless otherwise specified.
PARAMETERS
DC CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage
Offset Voltage Tempco
Input Bias Current
Input Bias Current
Input Offset Current
Input Offset Current
Positive Supply Current
Negative Supply Current
Positive Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Input Common Mode Range
Latch Enable
Common Mode Range
Open Loop Gain
Differential Input Resistance
Input Capacitance
Power Supply Sensitivity
Common Mode Rejection Ratio
Power Dissipation
Power Dissipation
Output High Level
Output Low Level
AC CHARACTERISTICS
Propagation Delay
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Fall Time
Slew Rate
Bandwidth
1
R
S
= Source impedance
TEST
CONDITIONS
V
IN
,
CM
=0, R
S
=0 Ohms
1
V
IN
,
CM
=0, R
S
=0 Ohms
1
T
MIN
<T
A
<T
MAX
TEST
LEVEL
I
IV
V
I
IV
I
IV
I
I
IV
IV
V
IV
V
V
V
V
V
I
I
I
I
IV
V
V
V
V
V
V
V
V
SPT9689A
MIN TYP MAX
–10
–15
±3.0
10
SPT9689B
MIN TYP MAX
–25
–30
±12
±15
40
±8
±12
±2.0
±4.0
18
40
5.0
–5.2
25
30
±25
±38
±5.0
±7.0
35
60
5.25
–5.45
+4.0
0
66
500
0.6
70
70
350
400
–1.00
–1.95
750
150
500
500
0
180
80
10
900
UNITS
mV
mV
µV/°C
µA
µA
µA
µA
mA
mA
V
V
V
V
dB
kΩ
pF
dB
dB
mW
mW
V
V
ps
ps
ps
ps
ps
ps
ps
V/ns
MHz
T
MIN
<T
A
<T
MAX
T
MIN
<T
A
<T
MAX
Dual
Dual
4.75
–4.95
–2.5
–2.0
±4.5
15
10
±8
±25
±12
±38
±1.0 ±3.0
±2.0 ±5.0
18
30
40
55
5.0 5.25
–5.2 –5.45
+4.0
0
66
500
0.6
70
70
350
400
4.75
–4.95
–2.5
–2.0
V
CM
=–2.5 to +4.0
Dual, Without Load
Dual, With Load
ECL 50 Ohms to –2 V
ECL 50 Ohms to –2 V
20 mV O.D.
250 mV O.D.
–1.00
–1.95
650
150
500
500
0
180
80
10
900
425
550
–.81
–1.54
850
300
600
475
550
–.81
–1.54
950
300
600
20% to 80%
20% to 80%
–3 dB
SPT9689
2
2/20/01
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25 °C. Parameter is guaranteed
over specified temperature range.
TIMING INFORMATION
The timing diagram for the comparator is shown in figure
1. If LE is high and LE low in the SPT9689, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or Q). The input signal must
be maintained for a time t
S
(set-up time) before the LE fall-
ing edge and LE rising edge and held for time t
H
after the
Figure 1 – Timing Diagram
Latch Enable
Latch Enable
t
S
Differential
Input Voltage
t
H
falling edge for the comparator to accept data. After t
H
, the
output ignores the input status until the latch is strobed
again. A minimum latch pulse width of t
pL
is needed for
strobe operation, and the output transitions occur after a
time of t
pLOH
or t
pLOL
.
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before t
S
will be detected and held;
those occurring after t
H
will not be detected. Changes
between t
S
and t
H
may not be detected.
50%
t
pL
V
OD
t
pdL
t
pLOH
V
REF
± V
OS
Output Q
50%
50%
Output Q
t
pdH
t
pLOL
V
IN
+=100 mV (p-p), V
OD
=20 mV
SPT9689
3
2/20/01
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition
t
pdL
INPUT TO OUTPUT LOW DELAY – the propagation
delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition
V
OD
VOLTAGE OVERDRIVE – the difference between
the differential input and reference input voltages
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
t
H
MINIMUM HOLD TIME – the minimum time after the
negative transition of the Latch Enable signal that
the input signal must remain unchanged in order to
be acquired and held at the outputs
MINIMUM LATCH ENABLE PULSE WIDTH – the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
MINIMUM SET-UP TIME – the minimum time before
the negative transition of the Latch Enable signal
that an input signal change must be present in order
to be acquired and held at the outputs
t
pL
t
S
GENERAL INFORMATION
The SPT9689 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.
The SPT9689 has a complementary latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
The negative common mode voltage is –2.5 V. The posi-
tive common mode voltage is +4.0 V.
The dual comparators share the same V
CC
and V
EE
con-
nections but have separate grounds for each comparator
to achieve high crosstalk rejection.
Figure 2 – Internal Function Diagram
Q
V
IN
V
IN
+
PRE
AMP
LATCH
ECL
OUT
Q
REF
1
REF
2
CLK
BUF
V
EE
V
CC
GND
LE
LE
SPT9689
4
2/20/01
TYPICAL PERFORMANCE CHARACTERISTICS
PROPAGATION DELAY VS OVERDRIVE VOLTAGE
800
.90
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
750
1.10
PROPAGATION DELAY TIME (ps)
700
OUTPUT RISE AND FALL (V)
1.30
650
1.50
600
1.70
550
500
0
20
1.90
OVERDRIVE (mV)
40
60
80
100
400
500
600
700
800
900
TIME (ps)
RISE TIME VS TEMPERATURE
280
FALL TIME VS TEMPERATURE
260
240
220
FALL TME (ps)
RISE TIME (ps)
200
180
160
140
120
100
80
60
-50
0
+50
+100
+150
50
0
+50
+100
+150
TEMPERATURE (°C)
TEMPERATURE (°C)
HYSTERESIS VS
D
LATCH
11
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
20
9
16
C
55 °
T=-
7
INPUT BIAS CURRENT (µA)
HYSTERESIS (mV)
12
5
T=
8
+25
°C
+
T=
4
125
°C
3
1
0
10
20
30
40
50
0
3.0
2.0
1.0
0.0
+1.0
+2.0
+3.0
+4.0
+5.0
D
LATCH = VLE VLE (mV)
COMMON MODE VOLTAGE (V)
SPT9689
5
2/20/01
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
