19-1745; Rev 3; 8/10
KIT
ATION
EVALU
BLE
AVAILA
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
General Description
Features
o
Single 3.0V Operation
o
Excellent Dynamic Performance
59.5dB SNR at f
IN
= 20MHz
74dBc SFDR at f
IN
= 20MHz
o
Low Power
19mA (Normal Operation)
5μA (Shutdown Mode)
o
Fully Differential Analog Input
o
Wide 2V
p-p
Differential Input Voltage Range
o
400MHz -3dB Input Bandwidth
o
On-Chip 2.048V Precision Bandgap Reference
o
CMOS-Compatible Three-State Outputs
o
32-Pin TQFP Package
o
Evaluation Kit Available
MAX1444
The MAX1444 10-bit, 3V analog-to-digital converter
(ADC) features a pipelined 10-stage ADC architecture
with fully differential wideband track-and-hold (T/H)
input and digital error correction incorporating a fully
differential signal path. This ADC is optimized for low-
power, high dynamic performance applications in
imaging and digital communications. The MAX1444
operates from a single 2.7V to 3.6V supply, consuming
only 57mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differ-
ential input stage has a 400MHz -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1444 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible refer-
ence structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Higher speed, pin-compatible versions of the MAX1444
are also available. Please refer to the MAX1446 data
sheet (60Msps) and the MAX1448 data sheet
(80Msps).
The MAX1444 has parallel, offset binary, CMOS-com-
patible three-state outputs that can be operated from
1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5x5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
Ordering Information
PART
MAX1444EHJ
MAX1444EHJ/V+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
32 TQFP
/V Denotes an automotive qualified part.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
REFOUT
TOP VIEW
REFIN
REFP
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
REFN
COM
V
DD
GND
GND
IN+
IN-
GND
1
2
3
4
5
6
7
8
GND
D0
D1
D2
26
32
31
30
29
28
27
D3
25
24 D4
23 OGND
22 T.P.
21 OV
DD
20 D5
19 D6
18 D7
17 D8
16
D9
MAX1444
9
V
DD
10
V
DD
11
GND
12
CLK
13
PD
14
GND
15
OE
Functional Diagram appears at end of data sheet.
TQFP
1
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1444
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND........................-0.3V to (V
DD
+ 0.3V)
OE,
PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C).....1495.3mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V; OV
DD
= 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V; REFOUT connected to
REFIN through a 10kΩ resistor; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 40MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
cal values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Differential Range
Common-Mode
Voltage Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
(f
CLK
= 40MHz, 4096-point FFT)
f
IN
= 7.51MHz
Signal-to-Noise Ratio
SNR
f
IN
= 19.91MHz
f
IN
= 39.9MHz (Note 1)
Signal-to-Noise + Distortion
(Up to 5th harmonic)
f
IN
= 7.51MHz
SINAD
f
IN
= 19.91MHz
f
IN
= 39.9MHz (Note 1)
f
IN
= 7.51MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 19.91MHz
f
IN
= 39.9 MHz (Note 1)
67
66
57
56.1
57.5
56.3
59.5
59.5
58.5
59.4
59
58.3
75
74
72.5
dBc
dB
dB
f
CLK
40
5.5
MHz
Cycles
V
DIFF
V
COM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±0.5
50
5
V
V
kΩ
pF
T
A
≥
+25°C
INL
DNL
f
IN
= 7.51MHz, T
A
≥
+25°C
f
IN
= 7.51MHz, no missing codes
guaranteed
10
±0.6
±0.4
<±0.1
0
±1.9
±1.0
±1.7
±2
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1444
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V; OV
DD
= 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V; REFOUT connected to
REFIN through a 10kΩ resistor; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 40MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
cal values are at T
A
= +25°C.)
PARAMETER
Third-Harmonic Distortion
SYMBOL
HD3
CONDITIONS
f
IN
= 7.51MHz
f
IN
= 19.91MHz
f
IN
= 39.9MHz (Note 1)
Two-Tone Intermodulation
Distortion
IMD
f
1
= 11.5MHz at -6.5dBFS
f
2
= 13.5MHz at -6.5dBFS
(Note 2)
f
1
= 11.5MHz at -6.5dBFS
f
2
= 13.5MHz at -6.5dBFS
(Note 2)
f
IN
= 7.51MHz
THD
f
IN
= 19.91MHz
f
IN
= 39.9MHz (Note 1)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= 2.048V)
REFIN Input Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
V
REFIN
V
REFP
V
REFN
V
COM
ΔV
REF
R
REFIN
ΔV
REF
= V
REFP
- V
REFN
, T
A
≥
+25°C
0.98
2.048
2.012
0.988
V
DD
/ 2
1.024
>50
1.07
V
V
V
V
V
MΩ
REFOUT
TC
REF
2.048
±1%
60
1.25
V
ppm/°C
mV/mA
IN+ = IN- = COM
FPBW
t
AD
t
AJ
For 1.5
×
full-scale input
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
TYP
-75
-74
-72.5
-76
dBc
dBc
MAX
UNITS
Third-Order Intermodulation
Distortion
IM3
-76
-73.8
-72.2
-70
500
400
1
2
2
±1
±0.25
0.2
-65
-65
dBc
Total Harmonic Distortion
(First 4 Harmonics)
dBc
MHz
MHz
ns
ps
RMS
ns
%
Degrees
LSB
RMS
_______________________________________________________________________________________
3
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1444
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V; OV
DD
= 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V; REFOUT connected to
REFIN through a 10kΩ resistor; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 40MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
cal values are at T
A
= +25°C.)
PARAMETER
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
C
IN
ΔV
REF
V
COM
ΔV
REF
= V
REFP
- V
REFN
Measured between REFP and COM
and REFN and COM
CONDITIONS
MIN
TYP
5
-250
250
-5
MAX
UNITS
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range
4
15
1.024
±10%
V
DD
/ 2
±10%
V
COM
+
ΔV
REF
/
2
V
COM
-
ΔV
REF
/
2
0.8
×
V
DD
0.8
×
OV
DD
0.2
×
V
DD
0.2
×
OV
DD
kΩ
pF
V
V
REFP Input Voltage
V
REFP
V
REFN Input Voltage
DIGITAL INPUTS (CLK, PD,
OE)
V
REFN
V
CLK
Input High Threshold
V
IH
PD,
OE
CLK
Input Low Threshold
V
IL
PD,
OE
V
V
4
_______________________________________________________________________________________
10-Bit, 40Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1444
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V; OV
DD
= 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= 2.048V; REFOUT connected to
REFIN through a 10kΩ resistor; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 40MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typi-
cal values are at T
A
= +25°C.)
PARAMETER
Input Hysteresis
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE
Fall to Output Enable
OE
Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-up Time
t
DO
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 25ns
Figure 6, clock period 25ns
(Note 4)
5
10
15
12.5
±3.8
12.5
±3.8
1.7
8
ns
ns
ns
ns
ns
µs
V
DD
OV
DD
I
VDD
I
OVDD
PSRR
Operating, f
IN
= 19.91MHz at -0.5dBFS
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
IN
= 19.91MHz at -0.5dBFS
Shutdown, clock idle, PD =
OE
= OV
DD
Offset
Gain
2.7
1.7
3.0
3.0
19
4
4.5
1
±0.1
±0.1
20
3.6
3.6
27
15
V
V
mA
µA
mA
µA
mV/V
%/V
V
OL
V
OH
I
LEAK
C
OUT
I
SINK
= 200μA
I
SOURCE
= 200μA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
-
0.2
±10
0.2
V
V
µA
pF
SYMBOL
V
HYST
I
IH
I
IL
C
IN
V
IH
= V
DD
= OV
DD
V
IL
= 0V
5
CONDITIONS
MIN
TYP
0.1
±5
±5
MAX
UNITS
V
µA
pF
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
, V
IL
.
Note 4:
REFIN is driven externally. REFP, COM, and REFN are left open while powered down.
_______________________________________________________________________________________
5
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