74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
Rev. 02 — 17 October 2007
Product data sheet
1. General description
The 74ALVC374 is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
The 74ALVC374 is functionally identical to the 74ALVC574, but has a different pin
arrangement.
2. Features
s
s
s
s
s
s
s
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A 115-A exceeds 200 V
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ALVC374D
−40 °C
to +85
°C
SO20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
SOT764-1
Type number
74ALVC374PW
−40 °C
to +85
°C
74ALVC374BQ
−40 °C
to +85
°C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
1
11
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna891
EN
C1
2
5
6
9
12
15
16
19
mna196
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
17
18
4
7
8
13
14
1D
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ALVC374_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 17 October 2007
2 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
mna892
Fig 3. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4. Logic diagram
74ALVC374_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 17 October 2007
3 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
Q0
D0
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aad040
2
3
4
5
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
CP 11
D1
Q1
Q2
D2
D3
Q3
6
7
8
9
GND 10
GND
(1)
374
1
OE
374
GND 10
001aad088
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
D[0:7]
CP
OE
Q[0:7]
V
CC
GND
Pin description
Pin
3, 4, 7, 8, 13, 14, 17, 18
11
1
2, 5, 6, 9, 12, 15, 16, 19
20
10
Description
data input
clock input (LOW to HIGH, edge-triggered)
output enable input (active LOW)
3-state flip-flop output
supply voltage
ground (0 V)
74ALVC374_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 17 October 2007
4 of 17
NXP Semiconductors
74ALVC374
Octal D-type flip-flop; positive-edge trigger; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable
outputs
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑
= LOW to HIGH clock transition
Operating mode
Internal flip-flop Output
CP
↑
↑
↑
↑
Dn
l
h
l
h
L
H
L
H
Qn
L
H
Z
Z
L
L
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
power-down mode, V
CC
= 0 V
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[2]
[1] [2]
Conditions
V
I
< 0 V
Min
−0.5
−50
−0.5
-
−0.5
−0.5
−0.5
-
-
−100
−65
Max
+4.6
-
+4.6
±50
V
CC
+ 0.5
+4.6
+4.6
±50
100
-
+150
500
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
°C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
−40 °C
to +85
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
74ALVC374_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 17 October 2007
5 of 17
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