PTN3356R1
ROM-based low-power DisplayPort to VGA adapter
Rev. 2.2 — 16 August 2016
Product data sheet
1. General description
PTN3356R1 is a ROM-based DisplayPort to VGA adapter optimized primarily for
motherboard applications, to convert a DisplayPort signal from the chip set to an analog
video signal that directly connects to the VGA connector. PTN3356R1 integrates a
DisplayPort receiver, a high-speed triple video digital-to-analog converter that supports a
wide range of display resolutions, for example, VGA to WUXGA (see
Table 8).
PTN3356R1 supports two DisplayPort lanes operating at either 2.7 Gbit/s or 1.62 Gbit/s
per lane.
PTN3356R1 supports I
2
C-bus over AUX per
DisplayPort standard
(Ref.
1),
and bridges
the VESA DDC channel to the DisplayPort Interface.
PTN3356R1 is powered from a 3.3 V power supply and consumes approximately 200 mW
of power for video streaming in WUXGA resolution and 410
W
of power in Low-power
mode. The VGA output is powered down when there is no valid DisplayPort source data
being transmitted. PTN3356R1 also aids in monitor detection by performing load sensing
on RGB lines and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA-compliant DisplayPort converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 10
9
DisplayPort Link down-spreading supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I
2
C-bus over AUX CH syntax
Active HIGH Hot Plug Detect (HPD) signal to the source
2.2 VESA-compliant eDP extensions
Supports Alternate Scrambler Seed Reset (ASSR)
Supports Alternate Enhanced Framing mode - Enhanced Framing
2.3 DDC channel output
I
2
C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see
Ref. 2)
NXP Semiconductors
PTN3356R1
ROM-based low-power DP to VGA adapter
2.4 Analog video output
VSIS 1.2 compliance (Ref.
3)
for supported video output modes
Analog RGB current-source outputs
3.3 V VSYNC and HSYNC outputs
Pixel clock up to 240 MHz
Triple 8-bit Digital-to-Analog Converter (DAC)
Direct drive of double terminated 75
load with standard 700 mV (peak-to-peak)
signals
2.5 General features
Monitor presence detection through load detection scheme. Connection/disconnection
reported via HPD IRQ and DPCD update.
Wide set of display resolutions are supported
1
:
1920
1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate
2048
1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate
2048
1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate
UXGA: 1600
1200, 60 Hz, 162 MHz pixel clock rate
SXGA: 1280
1024, 60 Hz, 108 MHz pixel clock rate
XGA: 1024
768, 60 Hz, 65 MHz pixel clock rate
SVGA: 800
600, 60 Hz, 40 MHz pixel clock rate
VGA: 640
480, 60 Hz, 25 MHz pixel clock rate
Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel
clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp
Bits per color (bpc) supported
1
6, 8 bits supported
10, 12, 16 bits supported by truncation to 8 MSBs
All VGA colorimetry formats (RGB) supported
Power modes (when the application design is as per
Figure 4)
Active-mode power consumption: ~200 mW at WUXGA, 1920
1200, 60 Hz
(18 bpc)
410
W
at Low-power mode
Supports flexible choice of timing reference
On-board oscillator with external crystal, ceramic resonator
Different frequencies supported: 24 MHz, 25 MHz, 27 MHz
ESD protection: 7 kV HBM
Single power supply (3.3 V) for easy integration in the platforms
Commercial temperature range: 0
C
to 85
C
32-pin HVQFN, 5 mm
5 mm
0.85 mm (nominal); 0.5 mm pitch; lead-free package
1.
Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane
DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
PTN3356R1
Product data sheet
Rev. 2.2 — 16 August 2016
2 of 38
NXP Semiconductors
PTN3356R1
ROM-based low-power DP to VGA adapter
3. Applications
Notebook computers, tablets and desktop PCs
Dongles, adapters, docking stations
4. Ordering information
Table 1.
Ordering information
Topside mark
356R1
Package
Name
PTN3356R1BS
HVQFN32
Description
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; 5
5
0.85 mm
[1]
Version
SOT617-3
Type number
[1]
Maximum height is 1 mm.
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PTN3356R1BSMP
Package
Packing method
Minimum
order
quantity
Temperature
Type number
PTN3356R1BS
HVQFN32
Reel 13” Q2/T3 *standard mark 6000
SMD dry pack
T
amb
= 0
C
to +85
C
PTN3356R1
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2.2 — 16 August 2016
3 of 38
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Product data sheet
Rev. 2.2 — 16 August 2016
4 of 38
PTN3356R1
5. Functional diagram
NXP Semiconductors
PTN3356R1
CFG3, CFG5,
TESTMODE
RX PHY
ANALOG
SUBSYSTEM
DIFF CDR,
RCV S2P
RX PHY DIGITAL
DE-SCRAM
ISOCHRONOUS LINK
R[7:0]
INTERFACE DE-SKEWING
G[7:0]
MAIN
STREAM
B[7:0]
H, V
sync
VGA
OUTPUT
DPCD
REGISTERS
CONTROL
ROM
MCU
VIDEO DAC SUBSYSTEM
MONITOR
PRESENCE
DETECT
DAC
DAC
DAC
RED
GRN
BLU
HSYNC
VSYNC
10b/8b
ML0_P, ML0_N
TIME
CONV.
TIMING RECOVERY
V
bias
DIFF CDR,
RCV S2P
DE-SCRAM
10b/8b
ML1_P, ML1_N
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
V
bias
RCV
MANCHESTER
CODEC
AUX_P, AUX_N
DRV
AUX COMMAND
LEVEL MODULE
I
2
C-BUS
MASTER
DDC_SCL
DDC_SDA
HPD
V
bias
RX DIGITAL SUBSYSTEM
OSC_IN
OSC_OUT
RSET
RST_N
CFG1, CFG2
aaa-013783
ROM-based low-power DP to VGA adapter
Fig 1.
Functional diagram
PTN3356R1
NXP Semiconductors
PTN3356R1
ROM-based low-power DP to VGA adapter
6. Pinning information
6.1 Pinning
27 VDDA15_DAC
29 TESTMODE
26 OSC_OUT
28 VDDD15
30 PVDD33
terminal 1
index area
VDDA33_DNW 1
AUX_P 2
AUX_N 3
ML0_P 4
ML0_N 5
VDDA15_DP 6
ML1_P 7
ML1_N 8
GND
(1)
RST_N 10
CFG1 12
CFG5 13
CFG3 14
CFG2 15
VDDE33_IO 9
DDC_SCL 16
HPD 11
25 OSC_IN
24 RED
23 RSET
22 GRN
21 BLU
20 HSYNC
19 VSYNC
18 DDC_SDA
17 VDDE33_IO
31 SWOUT
32 PGND
PTN3356R1
Transparent top view
aaa-013784
(1) Exposed die pad.
Fig 2.
Pin configuration for HVQFN32
6.2 Pin description
Table 3.
Symbol
VDDA33_DNW
AUX_P
AUX_N
ML0_P
ML0_N
VDDA15_DP
ML1_P
ML1_N
Pin description
Pin
1
2
3
4
5
6
7
8
Type
power
self-biasing differential
input
self-biasing differential
input
self-biasing differential
input
self-biasing differential
input
power
self-biasing differential
input
self-biasing differential
input
Description
3.3 V power supply
DisplayPort AUX channel positive input
DisplayPort AUX channel negative input
DisplayPort Main Link lane 0 positive input
DisplayPort Main Link lane 0 negative input
1.5 V power supply for DisplayPort PHY; power provided to this pin
from SWOUT pin
DisplayPort Main Link lane 1 positive input
DisplayPort Main Link lane 1 negative input
PTN3356R1
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 2.2 — 16 August 2016
5 of 38
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