Supertex inc.
High-Voltage,
Current-Mode PWM Controller
Features
►
►
►
►
►
►
10 to 450V input voltage range
<1.3mA supply current
>1.0MHz clock
>20:1 dynamic range @ 500KHz
99% Maximum duty cycle version
Low internal noise
HV9123
Applications
►
►
►
►
►
Off-line high frequency power supplies
Universal input power supplies
High density power supplies
Very high efficiency power supplies
Extra wide load range power supplies
General Description
The Supertex HV9123 is a Switch Mode Power Supply
(SMPS) controller subsystem that can start and run
directly from almost any DC input, from a 12V battery
to a rectified and filtered 240VAC line. It contains all the
elements required to build a single-switch converter except
for the switch, magnetic assembly, output rectifier(s) and
filter(s).
A unique input circuit allows the HV9123 to self-start directly
from a high voltage input, and subsequently take the power
to operate from one of the outputs of the converter it is
controlling, allowing very efficient operation while maintaining
input-to-output galvanic isolation limited in voltage only by
the insulation system of the associated magnetic assembly.
A ±2% internal bandgap reference, internal operational
amplifier, very high speed comparator, and output buffer
allow production of rugged, high performance, high efficiency
power supplies of 50W or more, which can still be over 80%
efficient at outputs of 1.0W or less. The wide dynamic range of
the controller system allows designs with extremely wide line
and load variations with much less difficulty and much higher
efficiency than usual. The exceptionally wide input voltage
range also allows better usage of energy stored in input
dropout capacitors than with other PWM ICs. Remote on/off
controls allow either latching or nonlatching remote shutdown.
During shutdown, the power required is under 6.0mW.
For detailed circuit and application information, please
refer to application notes AN-H13, AN-H21 to AN-H24.
Functional Block Diagram
15 (19)
FB
COMP DISCHARGE
Error
Amplifier
11 (14)
–
+
4V
REF
GEN
16 (20)
7 (9)
1 (3)
–
+
8.1V
8.6V
Current
Sources
To
Internal
Circuits
2V
–
+
+
–
1.2V
OSC
IN
OSC
OUT
8 (10)
OSC
Modulator
Comparator
To VDD
R
S
Current Limit
Comparator
Q
5 (6)
OUTPUT
VREF
BIAS
VDD
+VIN
6 (8)
-VIN
4 (5)
SENSE
12 (16)
SHUTDOWN
13 (17)
RESET
V
DD
–
+
Undervoltage
Comparator
Q
S
R
Note:
Pin numbers in parentheses are for PLCC package.
Doc.# DSFP-HV9123
B060412
Pre-regulator/Startup
Supertex inc.
www.supertex.com
HV9123
Ordering Information
Part Number
HV9123NG-G
HV9123NG-G M934
HV9123P-G
HV9123PJ-G
HV9123PJ-G M910
Package Options
16-Lead SOIC
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC*
20-Lead PLCC*
Packing
45/Tube
2500/Reel
24/Tube
48/Tube
1000/Reel
16-Lead SOIC (NG)
2
1
20
Pin Configurations
1
16
1
16
4
16-Lead PDIP (P)
-G Indicates package is RoHS compliant (‘Green’)
*
Obsolescence notice issued for the product in the 20-Lead PLCC package.
Typical Thermal Resistance
Package
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC
θ
ja
83
O
C/W
51 C/W
O
20-Lead PLCC (PJ)
Product Marking
Top Marking
YWW
HV9123NG
66
O
C/W
LLLLLLLL
Bottom Marking
Absolute Maximum Ratings
Parameter
Input voltage, V
IN
Device supply voltage, V
DD
Logic input voltage
Linear input voltage
Preregulator input current, I
IN
(continuous)
Operating junction temperature (T
J
)
Storage temperature
Power dissipation:
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC
900mW
1000mW
1400mW
Value
450V
15.5V
-0.3V to V
DD
+0.3V
-0.3V to V
DD
+0.3V
2.5mA
150
O
C
-65
O
C to +150
O
C
CCCCCCCCC AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead SOIC (NG)
Top Marking
H V9 123 P
YYWW
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead PDIP (P)
Top Marking
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
YY = Year Sealed
WW = Week Sealed
HV9123PJ
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
YYWW AAA
CCCCCCCCCCC
*May be part of top marking
Package may or may not include the following marks: Si or
20-Lead PLCC (PJ)
Doc.# DSFP-HV9123
B060412
2
Supertex inc.
www.supertex.com
HV9123
Electrical Characteristics
Sym
Parameter
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, Discharge = -V
IN
= 0V, R
BIAS
= 390KΩ, R
OSC
= 330KΩ, T
A
= 25°C.)
#
Min
3.92
3.84
15
-
-
1.0
80
160
-
-
95
-
-
-
Typ
4.00
4.00
30
125
0.25
3.0
100
200
-
170
97
225
-
80
Max
4.08
4.16
45
250
-
-
120
240
15
-
99
-
0
125
Units
Conditions
R
L
= 10MΩ
R
L
= 10MΩ, T
A
= -55 to 125
O
C
---
V
REF
= -V
IN
T
A
= -55 to 125°C
R
OSC
= 0Ω
R
OSC
= 330KΩ
R
OSC
= 150KΩ
9.5V < V
DD
< 13.5V
T
A
= -55 to 125°C
---
---
---
---
Reference
V
REF
Z
OUT
I
SHORT
ΔV
REF
f
MAX
f
OSC
ΔV
OSC
TC
OSC
Output voltage
Output impedance
Short circuit current
Change in V
REF
with temperature
Oscillator frequency
Initial accuracy
1
Voltage stability
Temperature coefficient
Maximum duty cycle
Deadtime
D
MIN
Minimum duty cycle
Maximum pulse width before
pulse drops out
Maximum input signal
Delay to output
-
#
-
#
-
-
-
-
#
#
#
-
#
V
KΩ
μA
mV/°C
MHz
KHz
%
ppm/°C
%
ns
%
ns
Oscillator
PWM
D
MAX
Current Limit
V
LIM
t
D
-
#
1.0
-
1.2
80
1.4
120
V
ns
V
FB
= 0V
V
SENSE
= 1.5V, V
COMP
≤ 2.0V
Error Amplifier
V
FB
I
IN
V
OS
A
VOL
GB
Z
OUT
I
SOURCE
I
SINK
PSRR
Feedback voltage
Input bias current
Input offset voltage
Open loop voltage gain
Unity gain bandwidth
Out impedance
Output source current
Output sink current
Power supply rejection
-
-
-
#
#
#
-
-
#
-1.4
0.12
3.92
-
60
1.0
4.00
25
80
1.3
see Fig. 1
-2.0
0.15
see Fig. 2
-
-
4.08
500
-
-
V
nA
-
dB
MHz
Ω
mA
mA
dB
V
FB
shorted to COMP
V
FB
= 4.0V
---
---
---
---
V
FB
= 3.4V
V
FB
= 4.5V
---
nulled during trim
Notes:
# Guaranteed by design.
1. Stray capacitance on OSC In pin must be ≤5pF.
Doc.# DSFP-HV9123
B060412
3
Supertex inc.
www.supertex.com
HV9123
Electrical Characteristics
(cont.)
Sym
+V
IN
+I
IN
V
TH
V
LOCK
Parameter
Input voltage
Input leakage current
V
DD
pre-regulator turn-off
threshold voltage
Undervoltage lockout
Supply current
Quiescent supply current
Nominal bias current
Operating range
SHUTDOWN delay
SHUTDOWN pulse width
RESET pulse width
Latching pulse width
Input low voltage
Input high voltage
Input current, input high voltage
Input current, input low voltage
(Unless otherwise specified, V
DD
= 10V, +V
IN
= 48V, Discharge = -V
IN
= 0V, R
BIAS
= 390KΩ, R
OSC
= 330KΩ, T
A
= 25°C.)
#
-
-
-
-
-
-
-
-
#
#
#
#
-
-
-
-
-
Min
10
-
8.0
7.0
-
-
-
9.0
-
50
50
25
-
7.0
-
-
V
DD
-0.25
V
DD
-0.3
-
-
-
-
-
-
-
-
Typ
-
-
8.7
8.1
0.75
0.55
20
-
50
-
-
-
-
-
1.0
-25
-
-
-
-
15
8.0
20
10
30
20
Max
450
10
9.4
8.9
1.3
-
-
13.5
100
-
-
-
2.0
-
5.0
-35
-
-
0.2
0.3
25
20
30
30
75
75
Units
V
μA
V
V
mA
mA
μA
V
ns
ns
ns
ns
V
V
μA
μA
V
V
V
V
Ω
Ω
Ω
Ω
ns
ns
Conditions
I
IN
< 10µA; V
CC
> 9.4V
V
DD
> 9.4V
I
PREREG
= 10µA
---
C
L
< 75pF
SHUTDOWN = -V
IN
---
---
C
L
= 500pF, V
SENSE
= -V
IN
---
---
SHUTDOWN and RESET low
---
---
V
IN
= V
DD
V
IN
= 0V
I
OUT
= 10mA
I
OUT
= 10mA,
T
A
= -55 to 125°C
I
OUT
= -10mA
I
OUT
= -10mA,
T
A
= -55 to 125°C
I
OUT
= ±10mA
I
OUT
= ±10mA,
T
A
= -55 to 125°C
C
L
= 500pF
C
L
= 500pF
Pre-regulator/Startup
Supply
I
DD
I
Q
I
BIAS
V
DD
t
SD
t
SW
t
RW
t
LW
V
IL
V
IH
I
IH
I
IL
Shutdown Logic
Output
V
OH
Output high voltage
-
-
V
OL
Output low voltage
Pull up
R
OUT
Output resistance
Pull down
Pull up
Pull down
t
R
t
F
Rise time
Fall time
-
-
-
-
-
#
#
Note:
# Guaranteed by design.
Doc.# DSFP-HV9123
B060412
4
Supertex inc.
www.supertex.com
HV9123
Test Circuits
+10V
(V
DD
)
Error Amp Z
OUT
1.0V swept 100Hz - 2.2MHz
0.1V swept 10Hz - 1.0MHz
PSRR
100K 1%
(FB)
60.4K
–
+
10.0V
100K1%
4.0V
–
+
Reference
GND
(-V
IN
)
0.1µF
V
1
Tektronix
P6021
(1 turn
secondary)
V
1
V
2
40.2K
V
2
Reference
0.1µF
Note:
Set feedback voltage so that V
COMP
= V
DIVIDE
± 1.0mV before connecting transformer.
Detailed Description
The preregulator/startup circuit for the HV9123 consists of
a high-voltage n-channel depletion-mode DMOS transistor
driven by an error amplifier to form a variable current path
between the VIN terminal and the VDD terminal. Maximum
current (about 20 mA) occurs when V
DD
= 0, with current re-
ducing as V
DD
rises. This path shuts off altogether when V
DD
rises to somewhere between 7.8 and 9.4V, so that if V
DD
is
held at 10 or 12V by an external source (generally the sup-
ply the chip is controlling), no current other than leakage is
drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
C
STORAGE
≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable. A common resistor divider string
is used to monitor V
DD
for both the undervoltage lockout cir-
cuit and the shutoff circuit of the high voltage FET. Setting
the undervoltage sense point about 0.6V lower on the string
than the FET shutoff point guarantees that the undervoltage
lockout always releases before the FET shuts off.
Preregulator
20µA, which can be set by a 390 to 510KΩ resistor if a 10V
V
DD
is used, or a 510 to 680KΩ resistor if V
DD
will be 12V. A
precision resistor is not required; ± 5% is fine.
Clock Oscillator
The clock oscillator of the HV9123 consists of a ring of
CMOS inverters, timing capacitors, and a capacitor dis-
charge FET. A single external resistor between the OSC IN
and OSC OUT pins is required to set oscillator frequency
(see graph). The discharge can either be connected to VSS
directly or connected to VSS through a resistor used to set
a dead time.
One difference exists between the Supertex HV9123 and
competitive 9123s: The oscillator is shut off when a shutoff
command is received. This saves about 150µA of quiescent
current, which aids in the construction of power supplies
to meet CCITT specification I-430, and in other situations
where an absolute minimum of quiescent power dissipation
is required.
Reference
Bias Circuit
The Reference of the HV9123 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufac-
ture so that the output of the error amplifier, when connected
in a gain of -1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a con-
sequence, even though the observed reference voltage of a
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
A ≈ 50KΩ resistor is placed internally between the output
of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error
An external bias resistor, connected between the bias pin
and VSS is required by the HV9123 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. Nominal external bias current requirement is 15 to
Doc.# DSFP-HV9123
B060412
5
Supertex inc.
www.supertex.com
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