19-5400; Rev 3; 9/04
IT
TION K
VALUA
E
BLE
AVAILA
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
General Description
The MAX1448 3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10-
stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully
differential signal path. The ADC is optimized for low-
power, high dynamic performance in imaging and digi-
tal communications applications. The converter
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a 59dB (typ) signal-to-
noise ratio (SNR) at a 20MHz input frequency. The fully
differential input stage has a -3dB 400MHz bandwidth
and may be operated with single-ended inputs. In addi-
tion to low operating power, the MAX1448 features a
5µA power-down mode for idle periods.
An internal 2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible refer-
ence structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Lower speed, pin-compatible versions of the MAX1448
are also available. Refer to the MAX1444 data sheet for
a 40Msps version and to the MAX1446 data sheet for a
60Msps version.
The MAX1448 has parallel, offset binary, CMOS-com-
patible three-state outputs that can be operated from
1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5mm x 5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
♦
Single 3.0V Operation
♦
Excellent Dynamic Performance
59dB SNR at f
IN
= 20MHz
74dBc SFDR at f
IN
= 20MHz
♦
Low Power
40mA (Normal Operation)
5µA (Shutdown Mode)
♦
Fully Differential Analog Input
♦
Wide 2V
P-P
Differential Input Voltage Range
♦
400MHz -3dB Input Bandwidth
♦
On-Chip 2.048V Precision Bandgap Reference
♦
CMOS-Compatible Three-State Outputs
♦
32-Pin TQFP Package
♦
Evaluation Kit Available (MAX1448 EV Kit)
Features
MAX1448
Ordering Information
PART
MAX1448EHJ
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Functional Diagram
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
CLK
MAX1448
CONTROL
V
DD
GND
IN+
T/H
IN-
PIPELINEADC
D
E
C
10
OUTPUT
DRIVERS
D9–D0
PD
REF
REFSYSTEM+
BIAS
OV
DD
OGND
REFOUT REFIN REFP
COM REFN
OE
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
MAX1448
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND..........................-0.3V to (V
DD
+ 0.3V)
OE,
PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.0V, OV
DD
= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V
REFIN
= 2.048V, REFOUT connected to
REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 83.3MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Differential Range
Common-Mode Voltage Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS (F
CLK
= 83.3MHZ, 4096-POINT FFT)
f
IN
= 7.47MHz
Signal-to-Noise Ratio
SNR
f
IN
= 20MHz
f
IN
= 39.9MHz (Note 1)
Signal-to-Noise + Distortion
(Up to 5th Harmonic)
f
IN
= 7.47MHz
SINAD
f
IN
= 20MHz
f
IN
= 39.9MHz (Note 1)
55.8
55.3
56.5
56
59.1
59
58.5
59
58.8
58
dB
dB
f
CLK
80
5.5
MHz
Cycles
V
DIFF
V
COM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±
0.5
25
5
V
V
kΩ
pF
T
A
≥
+25°C
INL
DNL
f
IN
= 7.47MHz, T
A
≥
+25°C
f
IN
= 7.47MHz, no missing codes
10
±0.7
±0.4
<±1
0
±2.2
±1.0
±1.7
±2
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V
REFIN
= 2.048V, REFOUT connected to
REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 83.3MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at T
A
= +25°C.)
PARAMETER
Spurious-Free Dynamic
Range
SYMBOL
f
IN
= 7.47MHz
SFDR
f
IN
= 20MHz
f
IN
= 39.9MHz (Note 1)
f
IN
= 7.47MHz
Third-Harmonic Distortion
Intermodulation Distortion
Two-Tone
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
(First 5 Harmonics)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
REFIN Input Voltage
Positive Reference Output Voltage
Negative Reference Output Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM Source
Current
REFOUT
TC
REF
2.048
±1%
60
1.25
V
REFIN
V
REFP
V
REFN
V
COM
∆V
REF
R
REFIN
I
SOURCE
∆V
REF
= V
REFP
- V
REFN
, T
A
≥
+25°C
0.98
2.048
2.012
0.988
V
DD
/ 2
1.024
>50
5
1.07
V
V
V
V
MΩ
mA
V
ppm/°C
mV/mA
IN+ = IN- = COM
FPBW
t
AD
t
AJ
For 1.5
×
full-scale input
HD3
f
IN
= 20MHz
f
IN
= 39.9MHz (Note 1)
IMD
TT
IM3
f
1
= 24MHz at -6.5dB FS, f
2
= 26MHz at
-6.5dB FS (Note 2)
f
1
= 24MHz at -6.5dB FS, f
2
= 26MHz at
-6.5dB FS (Note 2)
f
IN
= 7.47MHz
THD
f
IN
= 20MHz
f
IN
= 39.9MHz (Note 1)
Input at -20dB FS, differential inputs
Input at -0.5dB FS, differential inputs
CONDITIONS
MIN
61
61
TYP
74
74
73
-74
-74
-73
-74
-74
-72
-70
-69
500
400
1
2
2
±1
±0.25
0.2
MHz
MHz
ns
ps
RMS
ns
%
Degrees
LSB
RMS
-60
-60
dBc
dBc
dBc
dBc
dBc
MAX
UNITS
MAX1448
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
_______________________________________________________________________________________
3
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
MAX1448
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V
REFIN
= 2.048V, REFOUT connected to
REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 83.3MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at T
A
= +25°C.)
PARAMETER
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
C
IN
∆V
REF
V
COM
V
REFP
V
REFN
∆V
REF
= V
REFP
- V
REFN
Measured between REFP and COM and
REFN and COM
CONDITIONS
MIN
TYP
-250
250
-5
MAX
UNITS
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM )
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
DIGITAL INPUTS (CLK, PD,
OE)
CLK
Input High Threshold
V
IH
PD,
OE
CLK
Input Low Threshold
V
IL
PD,
OE
Input Capacitance
Input Hysteresis
Input Leakage
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
OL
V
OH
I
LEAK
C
OUT
I
SINK
= 200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
-
0.2
±10
0.2
V
V
µA
pF
C
IN
V
HYST
I
IH
I
IL
V
IH
= V
DD
= 0V
DD
V
IL
= 0
5
0.1
±5
±5
0.8 x
V
DD
0.8 x
OV
DD
0.2 x
OV
DD
0.2 x
OV
DD
pF
V
µA
4
15
1.024
± 10%
V
DD
/ 2
± 10%
V
COM
+
∆V
REF
/ 2
V
COM
-
∆V
REF
/ 2
kΩ
pF
V
V
V
V
V
V
4
_______________________________________________________________________________________
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, V
REFIN
= 2.048V, REFOUT connected to
REFIN through a 10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 83.3MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at T
A
= +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
V
DD
OV
DD
I
VDD
Operating, f
IN
= 20MHz at -0.5dB FS
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF, f
IN
= 20MHz at
-0.5dB FS
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE
Fall to Output Enable
OE
Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
t
DO
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 12ns
Figure 6, clock period 12ns
(Note 4)
5
10
15
6±1
6±1
1.5
8
ns
ns
ns
ns
ns
µs
PSRR
Offset
Gain
2.7
1.7
3.0
3.0
40
4
8
1
±0.2
±0.1
20
3.6
3.6
47
15
V
V
mA
µA
mA
µA
mV/V
%/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1448
Output Supply Current
I
OVDD
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
,V
IL
.
Note 4:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________
5
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