notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
1
IS42S16100C1
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A10 Row Address Input
A0-A7 Column Address Input
A11
Bank Select Address
DQ0 to DQ15
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
LDQM, UDQM x16 Input/Output Mask
V
dd
Power
Vss
Ground
V
ddq
Power Supply for I/O Pin
Vss
q
Ground for I/O Pin
NC
No Connection
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8
NC
NC
NC
DQ0
VDD
VDDQ DQ1
VSSQ DQ2
DQ4
DQ3
VDDQ DQ5
VSSQ DQ6
NC
VDD
LDQM
RAS
NC
NC
A0
A2
A3
DQ7
NC
WE
CAS
CS
NC
A10
A1
VDD
NC UDQM
NC
CKE
A11
A8
A6
VSS
CLK
NC
A9
A7
A5
A4
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
IS42S16100C1
PIN FUNCTIONS
Pin No.
20 to 24
27 to 32
Symbol
A0-A10
Type
Input Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOW during precharge command, the bank selected by A11 is precharged, but if A10 is
HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
These signals become part of the OP CODE during mode register set command input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register set
command input.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When is
CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend
mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device are
acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when
CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When
LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be
written to the device.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the “Command
Truth Table” item for details on device commands.
WE, in conjunction with
RAS
and
CAS,
forms the device command. See the “Command
Truth Table” item for details on device commands.
VddQ is the output buffer power supply.
Vdd is the device internal power supply.
GNdQ is the output buffer ground.
GNd is the device internal ground.
19
A11
Input Pin
16
34
CAS
CKE
Input Pin
Input Pin
35
18
CLK
CS
Input Pin
Input Pin
2, 3, 5, 6, 8, 9, 11 DQ0 to
12, 39, 40, 42, 43, DQ15
45, 46, 48, 49
14, 36
LDQM,
UDQM
DQ Pin
Input Pin
17
15
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
RAS
WE
VddQ
Vdd
GNdQ
GNd
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
3
IS42S16100C1
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
COMMAND
DECODER
&
CLOCK
GENERATOR
ROW DECODER
MODE
REGISTER
11
11
ROW
ADDRESS
BUFFER
2048
MEMORY CELL
ARRAY
11
BANK 0
DQM
SENSE AMP I/O GATE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
COLUMN
ADDRESS BUFFER
BURST COUNTER
COLUMN
ADDRESS LATCH
DATA IN
BUFFER
16
16
256
COLUMN DECODER
8
DQ 0-15
8
256
SENSE AMP I/O GATE
REFRESH
COUNTER
ROW DECODER
16
DATA OUT
BUFFER
16
MULTIPLEXER
11
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
2048
MEMORY CELL
ARRAY
VDD/VDDQ
GND/GNDQ
BANK 1
11
S16BLK.eps
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
08/24/09
IS42S16100C1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
dd max
V
ddq
V
iN
V
out
P
d max
I
cs
T
opr
T
stg
max
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
output Shorted Current
operating Temperature
Storage Temperature
Com
Ind.
Rating
Unit
–1.0 to +4.6 V
–1.0 to +4.6 V
–1.0 to +4.6 V
–1.0 to +4.6 V
1
50
0 to +70
-40 to +85
W
mA
°C
°C
–55 to +150 °C
DC RECOMMENDED OPERATING CONDITIONS
(2)
(
At T
a
= 0 to +70°C)
Symbol
V
dd
, V
ddq
V
ih
V
il
Parameter
Supply Voltage
Input High Voltage
(3)
Input Low Voltage
(4)
Min.
3.0
2.0
-0.3
Typ.
3.3
—
—
Max.
3.6
V
dd
+ 0.3
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS
(1,2)
(At T
a
= 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol
C
iN
1
C
iN
2
CI/O
Parameter
Input Capacitance: A0-A11
Input Capacitance: (CLK, CKE,
CS, RAS, CAS, WE, LDQM, UDQM)
Data Input/Output Capacitance: DQ0-DQ15
Typ.
—
—
—
Max.
4
4
5
Unit
pF
pF
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
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