74AUP1T98
Low-power configurable gate with voltage-level translator
Rev. 4 — 15 august 2012
Product data sheet
1. General description
The 74AUP1T98 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T98 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
2. Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 1.5
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1T98
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1T98GW
74AUP1T98GM
74AUP1T98GF
74AUP1T98GN
74AUP1T98GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
SOT1115
SOT1202
4. Marking
Table 2.
Marking
Marking code
aR
aR
aR
aR
aR
Type number
74AUP1T98GW
74AUP1T98GM
74AUP1T98GF
74AUP1T98GN
74AUP1T98GS
5. Functional diagram
3
4
B
1
Y
A
C
6
001aad987
Fig 1.
Logic symbol
74AUP1T98
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 august 2012
2 of 20
NXP Semiconductors
74AUP1T98
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
74AUP1T98
74AUP1T98
B
GND
1
2
6
5
C
GND
V
CC
A
A
3
001aah839
B
1
6
C
B
GND
74AUP1T98
1
2
3
6
5
4
C
V
CC
Y
2
5
V
CC
3
4
Y
A
4
Y
001aah840
001aah841
Transparent top view
Transparent top view
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
H
H
L
L
H
L
H
L
H = HIGH voltage level; L = LOW voltage level.
74AUP1T98
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 august 2012
3 of 20
NXP Semiconductors
74AUP1T98
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 6
see
Figure 7
see
Figure 7
see
Figure 8
see
Figure 8
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input MUX (inverting)
2-input NAND
2-input NOR with one input inverted
2-input AND with one input inverted
2-input NAND with one input inverted
2-input OR with one input inverted
2-input NOR
Buffer
Inverter
V
CC
B
Y
A
C
A
2
3
5
4
Y
001aad991
V
CC
1
A
C
Y
A
2
3
6
5
4
Y
001aad992
B
1
6
C
C
Fig 5.
2-input MUX (inverting)
Fig 6.
2-input NAND gate
V
CC
V
CC
A
C
A
C
1
2
Y
A
3
6
5
4
Y
001aad993
Y
C
B
C
B
C
Y
B
1
2
6
5
4
C
Y
3
Y
001aad994
Fig 7.
2-input AND gate with input A inverted or
2-input NOR gate with input C inverted
Fig 8.
2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
V
CC
B
B
C
Y
1
2
3
6
5
C
4
Y
3
001aad995
V
CC
C
1
Y
2
6
5
4
Y
001aad996
C
Fig 9.
2-input NOR gate
Fig 10. Buffer
74AUP1T98
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 august 2012
4 of 20
NXP Semiconductors
74AUP1T98
Low-power configurable gate with voltage-level translator
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aad997
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 package: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
2.3
0
0
0
40
Max
3.6
3.6
V
CC
3.6
+125
Unit
V
V
V
V
C
74AUP1T98
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 august 2012
5 of 20
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
