NCP6914
5 Channel PMIC: 1 DCDC
Converter and 4 LDOs
The NCP6914 integrated circuits are part of the ON Semiconductor
mini power management IC family (PMIC). They are optimized to
supply battery powered portable application sub−systems such as
camera function and microprocessors. These devices integrate 1 high
efficiency 800 mA Step−down DC to DC converter with DVS
(Dynamic Voltage Scaling) and four low−dropout (LDO) voltage
regulators in a WLCSP20 1.77 x 2.06 mm package.
Features
♦
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MARKING
DIAGRAM*
•
1 DCDC Converter (3 MHz, 1
mH/10 mF,
800 mA)
Peak Efficiency 95%
♦
Programmable Output Voltage from 0.6 V to 3.3 V by 12.5 mV
Steps
4 Low Noise − Low Dropout Regulators (300 mA)
♦
Programmable Output Voltage from 1.0 V to 3.3 V by 50 mV
Steps
♦
50
mV
rms
Typical Low Output Noise
Control
♦
400 kHz / 3.4 MHz I
2
C Compatible
♦
Hardware Enable Pin
♦
Power Good and Interrupt Output Pin
♦
External Synchronization
♦
Customizable Power Up Sequencer
Extended Input Voltage Range 2.3 V to 5.5 V
Optimized Power Efficiency
♦
72
mA
Very Low Quiescent Current at No Load
♦
Less than 1
mA
Off Mode Current
Small Footprint: Package 1.77 x 2.06 mm WLCSP
These are Pb−Free Devices
Cellular Phones
Digital Cameras
Personal Digital Assistant and Portable Media Player
GPS Systems
Battery or
System Supply
AVIN
1 .0 uF
WLCSP20
CASE 567CV
6914Ax
AWLYWW
G
•
x
•
A
WL
Y
WW
G
= A for NCP6914AA
= B for NCP6914AB
= D for NCP6914AD
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
(Pb−Free indicator, “G” or microdot “
G”,
may or may
not be present.)
1
2
3
4
A
VIN4
VIN3
VOUT3
VBG
Typical Applications
B
VOUT4
PG
AVIN
AGND
C
HWEN
SDA
SYNC
VOUT1
NCP6914
4.7 uF
B3
D1
PVIN1
System Supply
D
DCDC1 Out
10 uF
PVIN1
SCL
INTB
VIN12
AGND
100 nF
B4
Core
DCDC 1
800 mA
E2
E3
E1
SW1
1 uH
FB1
PGND1
VBG
A4
Power Up
Sequencer
Thermal
Protection
Processor or
System Supply
Processor
Interrupt
HWEN
INTB
SDA
Processor
I@C
SCL
SYNC
Power State
Indicator
PG
C1
D3
C2
D2
C3
C4
VOUT1
2 .2uF
E
LDO1 Out
PGND1
SW1
FB1
VOUT2
LDO 1
300 mA
D4
VIN12
Enabling
Interrupt
LDO 2
300 mA
System or
DCDC
Supply
LDO2 Out
2 .2uF
E4
VOUT2
A2
VIN3
VOUT3
VIN4
VOUT4
I
2
C
LDO 3
300 mA
System or
DCDC
Supply
LDO3 Out
System or
DCDC
Supply
2 .2uF
(Top View)
20−Pin 1.77 x 2.06 mm WLCSP, 0.40 mm Pitch
A3
A1
Clocking
Supply
Monitoring
LDO 4
300 mA
B2
B1
Rev 1. 00
LDO4 Out
2 .2 uF
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 35 of this data sheet.
Figure 1. Application Schematic
©
Semiconductor Components Industries, LLC, 2014
1
April, 2014 − Rev. 10
Publication Order Number:
NCP6914/D
NCP6914
AVIN
THERMAL
SHUTDOWN
PVIN1
SCL
SDA
SERIAL
INTERFACE
DCDC
800 mA
STEP−DOWN
CONVERTER
SW1
FB1
PGND1
HWEN
CONTROL
VLDO1
300 mA LDO
VOUT1
INTB
VIN12
VLDO2
300 mA LDO
VOUT2
PG
VBG
SYNC
UVLO
VREF
OSC
VLDO3
300 mA LDO
VIN3
VOUT3
VLDO4
300 mA LDO
VIN4
VOUT4
AGND
Figure 2. Functional Block Diagram
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2
NCP6914
1
2
3
4
A
VIN4
VIN3
VOUT3
VBG
B
VOUT4
PG
AVIN
AGND
C
HWEN
SDA
SYNC
VOUT1
D
PVIN1
SCL
INTB
VIN12
E
PGND1
SW1
FB1
VOUT2
Figure 3. Pin Out (Top View)
Table 1. PINOUT DESCRIPTION
Pin
POWER
B3
A4
B4
AVIN
VBG
AGND
Analog Input
Analog Output
Analog Ground
Analog Supply. This pin is the device analog and digital supply. A 1.0
mF
ceramic capacitor or larger
must bypass this input to ground. This capacitor should be placed as close as possible to this pin.
Reference Voltage. A 0.1
mF
ceramic capacitor must bypass this pin to the system ground.
Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
Name
Type
Description
CONTROL AND SERIAL INTERFACE
C1
C3
D2
C2
B2
D3
HWEN
SYNC
SCL
SDA
PG
INTB
Digital Input
Digital Input
Digital Input
Digital
Input/Output
Digital Output
Digital Output
Hardware Enable. Active high will enable the part. There is an internal pull down resistor on this pin.
External Synchronization Input.
I
2
C interface Clock.
I
2
C interface Data.
Power Good. Open drain output.
Interrupt. Open drain output.
DCDC CONVERTER
D1
E2
E3
E1
PVIN1
SW1
FB1
PGND1
Power Input
Power Output
Analog Input
Power
Ground
DCDC Power Supply. This pin must be decoupled to ground by a 4.7
mF
ceramic capacitor. This
capacitor should be placed as close as possible to this pin.
DCDC Switch Power. This pin connects the power transistors to one end of the inductor. Typical
application uses 1.0
mH
inductor; refer to application section for more information.
DCDC Feedback Voltage. This pin is the input to the error amplifier and must be connected to the
output capacitor.
DCDC Power Ground. This pin is the power ground and carries the high switching current. A high
quality ground must be provided to prevent noise spikes. A local ground plane is recommended to
avoid high−density current flow in a limited PCB track.
LDO REGULATORS
D4
C4
E4
A2
A3
A1
B1
VIN12
VOUT1
VOUT2
VIN3
VOUT3
VIN4
VOUT4
Power Input
Power Output
Power Output
Power Input
Power Output
Power Input
Power Output
LDO 1&2 Power Supply.
LDO 1 Output Power. This pin requires a 2.2
mF
decoupling capacitor.
LDO 2 Output Power. This pin requires a 2.2
mF
decoupling capacitor.
LDO 3 Power Supply.
LDO 3 Output Power. This pin requires a 2.2
mF
decoupling capacitor.
LDO 4 Power Supply.
LDO 4 Output Power. This pin requires a 2.2
mF
decoupling capacitor.
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NCP6914
Table 2. MAXIMUM RATINGS
(Note 1)
Symbol
V
A
Rating
Analog and power pins: AVIN, PVIN1, SW1, VIN12, VIN3, VIN4, VOUT1,
VOUT2, VOUT3, VOUT4, PG, INTB, FB1, VBG
Digital pins: SCL, SDA, HWEN, SYNC:
Input voltage
Input current
Human Body Model (HBM) ESD Rating (Note 2)
Machine Model (MM) ESD Rating (Note 2)
Latch up current: (Note 3)
All digial pins
All other pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
Value
−0.3 to + 6.0
Unit
V
V
DG
I
DG
ESD HBM
ESD MM
I
LU
−0.3 to V
A
+0.3
≤
6.0
10
2000
200
±10
±100
−65 to + 150
−40 to +150
Level 1
V
mA
V
V
mA
T
STG
T
JMAX
MSL
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltages are related to AGND.
2. ESD rated the following:
Human Body Model (HBM)
±2.0
kV per JEDEC standard: JESD22−A114.
Machine Model (MM)
±200
V per JEDEC standard: JESD22−A115.
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
AV
IN,
PV
IN
LDO
VIN
T
A
T
J
R
qJA
P
D
P
D
L
Co
Power Supply
LDO Input Voltage Range
Ambient Temperature Range
Junction Temperature Range (Note 6)
Thermal Resistance Junction−to−Ambient (Note 7)
Power Dissipation Rating (Note 8)
Power Dissipation Rating (Note 8)
Inductor for DCDC Converter (Note 5)
Output Capacitor for DCDC Converter (Note 5)
Output Capacitors for LDO (Note 5)
C
in
Input Capacitor for DCDC Converter (Note 5)
CSP−20 on Demo−board
T
A
≤
85°C
T
A
= 40°C
Parameter
Conditions
Min
2.3
1.7
−40
−40
−
−
−
0.47
−
1.20
−
Typ
−
−
25
25
60
660
1400
1
10
2.2
4.7
Max
5.5
5.5
+85
+125
−
−
−
2.2
−
−
−
Unit
V
V
°C
°C
°C/W
mW
mW
mH
mF
mF
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Refer to the Application Information section of this data sheet for more details.
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The R
qJA
is dependent of the PCB heat dissipation. Board used to drive this data was a NCP6914EVB board. It is a multilayer board with
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
8. The maximum power dissipation (P
D
) is dependent by input voltage, maximum output current and external components selected.
R
qJA
+
125
*
T
A
P
D
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NCP6914
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T
J
up to +125°C unless otherwise specified. AV
IN
= PV
IN1
= V
IN12
= V
IN3
= V
IN4
= 3.6 V (unless otherwise
noted). DCDC Output Voltage = 1.2 V, LDO1&2 = 1.8 V, LDO3&4 = 2.8 V, Typical values are referenced to T
J
= + 25°C and default
configuration (Note 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN − PVIN1
I
Q
Operating Quiescent Current
DCDC on − no load − no switching
LDOs off
T
A
= up to +85°C
DCDC on − no load − no switching
LDOs on − no load
T
A
= up to +85°C
DCDC Off
All LDOs on − no load
T
A
= up to +85°C
I
SLEEP
Product Sleep Mode Current
HWEN on
DCDC and all LDOs off
T
A
= up to +85°C
HWEN off
I
2
C interface disabled
V
IN
= 2.3 V to 5.5 V
T
A
= up to +85°C
−
32
70
mA
−
72
190
−
55
100
mA
−
7
15
mA
I
OFF
Product Off Current
−
0.1
2.0
mA
DCDC Converter
PV
IN
I
OUTMAX
D
VOUT
F
SW
R
ONHS
Input Voltage Range
Maximum Output Current
Output Voltage DC Error
Switching Frequency
P−Channel MOSFET On Res-
istance
From PVIN1 to SW1, T
A
= up to +85°C
Guarantee by design and
characterization, production tested at
Vin = 3.6 V
From SW1 to PGND1, T
A
up to 85°C
Guarantee by design and
characterization, production tested at
Vin=3.6 V
Open loop
2.3 V
≤
PV
IN
≤
5.5 V
I
OUT
from 300 mA to I
OUTMAX
I
OUT
= 300 mA
2.3 V
≤
V
IN
≤
5.5 V
Io = 300 mA, PWM mode
T
A
= up to +85°C
2.3
0.8
−1
2.7
−
−
0
−
5.5
−
1
3.3
V
A
%
MHz
−
230
−
mW
R
ONLS
N−Channel MOSFET On Res-
istance
−
200
−
mW
I
PK
Peak Inductor Current
Load Regulation
Line Regulation
1.0
−
−
−
1.3
5
0
100
−
7
1.6
−
−
−
1
−
A
mV/A
%/V
%
ms
W
D
t
START
R
DISDCDC
Maximum Duty Cycle
Soft−Start Time
DCDC Active Output Discharge
Time from I
2
C command ACK to
90% of Output Voltage
−
−
LDO1 AND LDO2
V
IN12
LDO1 and LDO2 input voltage
Range 300 mA load
Maximum Output Current
Short Circuit Protection
V
OUT
≤
1.3 V, I
OUT
= 300 mA
V
OUT
> 1.3 V, I
OUT
= 300 mA
1.7
V
out
+ V
DROP
300
360
−
−
−
−
5.5
5.5
−
700
V
mA
mA
I
OUTMAX1,2
I
SC1,2
9. Devices that use non−standard supply voltages which do not conform to the intent I
2
C bus system levels must relate their input levels
to the V
DD
voltage to which the pull−up resistors R
P
are connected.
10. Refer to the Application Information section of this data sheet for more details.
11. Guaranteed by design and characterized.
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