74LVC646AD-T: 产品描述Bus Transceivers OCTAL BUS INTERFACE TRANS/REG; 产品类别逻辑逻辑; 文件大小155KB，共23页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LVC646AD-T概述

Bus Transceivers OCTAL BUS INTERFACE TRANS/REG

74LVC646AD-T规格参数

参数名称	属性值
Source Url Status Check Date	2013-06-14 00:00:00
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	SOIC
包装说明	SOP,
针数	24
Reach Compliance Code	unknown
其他特性	WITH DIRECTION CONTROL
系列	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24
JESD-609代码	e4
长度	15.4 mm
负载电容（CL）	50 pF
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER
湿度敏感等级	1
位数	8
功能数量	1
端口数量	2
端子数量	24
最高工作温度	85 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
峰值回流温度（摄氏度）	260
传播延迟（tpd）	8.6 ns
认证状态	Not Qualified
座面最大高度	2.65 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1.2 V
标称供电电压 (Vsup)	2.7 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	NICKEL PALLADIUM GOLD
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	7.5 mm
Base Number Matches	1

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74LVC646A

Octal bus transceiver/register; 3-state

Rev. 5 — 28 March 2013

Product data sheet

1. General description

The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs,

D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly

from the internal registers. Data on the A or B bus is clocked in the internal registers, as

the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE)

and direction (DIR) inputs are provided to control the transceiver function. In the

transceiver mode, data present at the high-impedance port may be stored in either the A

or B register, or in both. With the select source inputs (SAB and SBA), stored and

real-time (transparent mode) data can be multiplexed. The direction (DIR) input

determines which bus receives data when OE is active (LOW). In the isolation mode (OE

= HIGH), A data may be stored in the B register and/or B data may be stored in the A

used to store and transmit data. Only one of the two buses A or B may be driven at a time.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Supply voltage range from 1.2 V to 3.6 V

CMOS low-power consumption

Direct interface with TTL levels

8-bit octal transceiver with D-type latch

Back-to-back registers for storage

Separate controls for data flow in each direction

Supports partial power-down applications; inputs/outputs are high-impedance when

= 0 V



Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C.

74LVC646AD-T相似产品对比

	74LVC646AD-T	74LVC646APW	74LVC646ADB	74LVC646ADB-T	74LVC646AD
描述	Bus Transceivers OCTAL BUS INTERFACE TRANS/REG			Bus Transceivers OCTAL BUS INTERFACE TRANS/REG	Bus Transceivers OCTAL BUS INTERFACE TRANS/REG
是否无铅	不含铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合	符合
零件包装代码	SOIC	TSSOP	SSOP	SSOP	SOIC
包装说明	SOP,	TSSOP, TSSOP24,.25	SSOP, SSOP24,.3	SSOP,	SOP, SOP24,.4
针数	24	24	24	24	24
Reach Compliance Code	unknown	unknown	compliant	unknown	unknown
其他特性	WITH DIRECTION CONTROL	WITH DIRECTION CONTROL	WITH DIRECTION CONTROL	WITH DIRECTION CONTROL	WITH DIRECTION CONTROL
系列	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 代码	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24	R-PDSO-G24
JESD-609代码	e4	e4	e4	e4	e4
长度	15.4 mm	7.8 mm	8.2 mm	8.2 mm	15.4 mm
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
湿度敏感等级	1	1	1	1	1
位数	8	8	8	8	8
功能数量	1	1	1	1	1
端口数量	2	2	2	2	2
端子数量	24	24	24	24	24
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SOP	TSSOP	SSOP	SSOP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
峰值回流温度（摄氏度）	260	260	260	260	260
传播延迟（tpd）	8.6 ns	8.6 ns	8.6 ns	8.6 ns	8.6 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.65 mm	1.1 mm	2 mm	2 mm	2.65 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
标称供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
表面贴装	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	1.27 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30
宽度	7.5 mm	4.4 mm	5.3 mm	5.3 mm	7.5 mm
Base Number Matches	1	1	1	1	1
控制类型	-	INDEPENDENT CONTROL	INDEPENDENT CONTROL	-	INDEPENDENT CONTROL
计数方向	-	BIDIRECTIONAL	BIDIRECTIONAL	-	BIDIRECTIONAL
最大I（ol）	-	0.024 A	0.024 A	-	0.024 A
封装等效代码	-	TSSOP24,.25	SSOP24,.3	-	SOP24,.4
电源	-	3.3 V	3.3 V	-	3.3 V
Prop。Delay @ Nom-Sup	-	7.8 ns	6.8 ns	-	6.8 ns
翻译	-	N/A	N/A	-	N/A
触发器类型	-	POSITIVE EDGE	POSITIVE EDGE	-	POSITIVE EDGE

74LVC646AD-T

74LVC646AD-T在线购买

74LVC646AD-T概述

74LVC646AD-T规格参数

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74LVC646AD-T相似产品对比

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