19-2713; Rev 1; 11/03
KIT
ATION
EVALU
BLE
AVAILA
12.5Gbps Settable Receive Equalizer
General Description
Features
o
Compensates Up to 30in (0.75m) of 6-mil FR-4
Transmission Line Loss
o
115mW Operating Power
o
Up to 12.5Gbps Data Rate
o
Compatible with 8B10B, 64B66B, and PRBS Data
o
Less than 30ps
P-P
Residual Jitter After
Equalization
o
3-Bit Equalization Level Select Input
o
3mm x 3mm Thin QFN Package
o
DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O
o
-40°C to +85°C Operation
o
+3.3V Core Supply Voltage
MAX3804
The MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter-
symbol interference. The MAX3804 can extend the practi-
cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal-
ization for 10.7Gbps signals is typically 24ps
P-P
on the
maximum path length.
The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm
✕
3mm package affords optimal placement and
routing flexibility. It has separate V
CC
connections for
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso-
lated supplies, providing independent DC-coupled inter-
facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con-
trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per-
formance over a wide range of data rates and formats.
Ordering Information
PART
MAX3804ETE
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
PACKAGE
CODE
Applications
OC-192 and 10Gb Ethernet Switches and Routers
OC-192 and 10Gb Ethernet Serial Modules
High-Speed Signal Distribution
16 Thin QFN
T1633F-3
(3mm x 3mm)
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
+1.8V
+2.5V
+3.3V
V
CC
10Gbps
SERIAL OPTICAL
MODULE SDO+
IN
SDO-
+3.3V
30in OF FR-4 STRIPLINE OR
MICROSTRIP TRANSMISSION LINE
V
CC
V
CC2
10Gbps
SERDES
SDI+
SDI-
V
CC1
V
CC
MAX3804
SDI+
SDI-
SDO+
SDO-
EQ1 EQ2 EQ3 GND
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12.5Gbps Settable Receive Equalizer
MAX3804
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
CC
) ............................................-0.5V to +4.0V
CML Supply Voltage (V
CC1
, V
CC2
) ............-0.5V to (V
CC
+ 0.5V)
Current at Serial Output (SDO+, SDO-) ............................±25mA
Input Voltage (SDI+, SDI-, EQ1,
EQ2, EQ3) ..............................................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
16-Lead Thin QFN-EP (derate 17.5mW/°C
above +85°C) ........................................................1398mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, V
CC1
= V
CC2
= +1.65V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= V
CC1
= V
CC2
= +3.3V,
and T
A
= +25°C, unless otherwise noted.)
PARAMETER
Supply Current
CML Input Differential
CML Input Common Mode
CML Input Termination
CML Input Return Loss
CML Output Differential
CML Output Impedance
CML Output Transition Time
Residual Jitter Output
(Total RJ, PWD, and PDJ)
LVTTL Input Current
LVTTL Input Low
LVTTL Input High
I
IH
, I
IL
V
IL
V
IH
2.0
t
R
, t
F
V
OUT
Single ended
20% to 80% (Notes 2, 6)
At 10.7Gbps (Notes 3, 4, 5, 6)
At 12.5Gbps (Notes 3, 4, 5, 6)
-30
24
17
SYMBOL
I
CC
V
IN
AC-coupled or DC-coupled (Note 1)
DC-coupled
Single ended
Up to 5GHz
400
42.5
400
V
CC1
- 0.4
42.5
50
10
500
50
600
57.5
35
30
30
+30
0.8
CONDITIONS
MIN
TYP
35
MAX
50
1200
V
CC1
+ 0.1
57.5
UNITS
mA
mV
P-P
V
Ω
dB
mV
P-P
Ω
ps
ps
P-P
µA
V
V
Note 1:
Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z
0
= 100Ω, 6-mil
microstrip in FR-4,
ε
r
= 4.5, and tan
δ
= 0.02, V
IN
= (SDI+ - SDI-).
Note 2:
Measured with 0000011111 pattern at 12.5Gbps.
Note 3:
Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-
sion line) and equalizer output. Total residual jitter is DJ
P-P
+ 14.2 x RJ
RMS
.
Note 4:
Measured at 10.7Gbps using a pattern of 100 ones, 2
7
PRBS, 100 zeros, 2
7
PRBS, and at 12.5Gbps using a K28.5 pattern.
Deterministic jitter at the input is from frequency-dependent, media-induced loss only.
Note 5:
V
IN
= 400mV
P-P
to 1200mV
P-P
, input path is 0 to 30in, 6-mil microstrip in FR-4,
ε
r
= 4.5, and tan
δ
= 0.02.
Note 6:
Guaranteed by design and characterization.
2
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
RESIDUAL JITTER
vs. INPUT AMPLITUDE
MAX3804 toc01
MAX3804 toc02
MAX3804
SUPPLY CURRENT vs. TEMPERATURE
85
V
CC
= V
CC1
= V
CC2
= 3.3V
70
SUPPLY CURRENT (mA)
35
30
RESIDUAL JITTER (ps
P-P
)
25
20
15
10
5
10
-40
-15
10
35
60
85
TEMPERATURE (°C)
0
400
RESIDUAL JITTER
vs. FR-4 PATH LENGTH
400mV
P-P
INPUT AMPLITUDE
2
7
PRBS WITH 100
CIDs AT 9.953Gbps
MAX3804 toc03
MAX3804 toc06
30in OF FR-4
TRANSMISSION LINE
2
7
PRBS WITH 100
CIDs AT 9.953Gbps
35
30
RESIDUAL JITTER (ps
P-P
)
25
20
15
10
5
0
3
9
15
K28.5 AT 12.5Gbps
55
40
K28.5 AT 12.5Gbps
RESIDUAL JITTER
= DJ
P-P
+ 14.2RJ
RMS
600
800
1000
1200
INPUT AMPLITUDE (mV
P-P
)
25
RESIDUAL JITTER
= DJ
P-P
+ 14.2RJ
RMS
21
27
FR-4 PATH LENGTH (in)
RESIDUAL JITTER
vs. EQUALIZATION SETTING
18in
31
RESIDUAL JITTER (ps
P-P
)
24in
27
6in
23
30in
RESIDUAL JITTER
DJ
P-P
+ 14.2RJ
RMS
MAX3804 toc04
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4
(2
7
PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc05
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4
(K28.5 AT 12.5Gbps)
35
60mV/
div
60mV/
div
19
3in
000
001
12in
010
011
15
400mV
P-P
, FR-4,
2
7
PRBS WITH 100
CIDs AT 10.7Gbps
100
101
110
111
16ps/div
16ps/div
EQUALIZATION SETTING (EQ3, EQ2, EQ1)
_______________________________________________________________________________________
3
12.5Gbps Settable Receive Equalizer
MAX3804
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
EQUALIZER INPUT EYE AFTER 30in OF FR-4
(2
7
PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc07
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(2
7
PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc08
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(K28.5 AT 12.5Gbps)
MAX3804 toc09
60mV/
div
60mV/
div
60mV/
div
16ps/div
16ps/div
16ps/div
EQUALIZER OUTPUT EYE AFTER 24ft
OF RG-188/U COAXIAL CABLE, SINGLE ENDED
(2
7
PRBS WITH 100 CIDs, 9.953Gbps)
MAX3804 toc10
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(2
7
PRBS WITH 100 CIDs AT 3.2Gbps)
MAX3804 toc11
60mV/
div
60mV/
div
20ps/div
60ps/div
4
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Pin Description
PIN
1, 4
2
3
5
6
7
8, 16
9, 12
10
11
13, 14
15
EP
NAME
V
CC1
SDI+
SDI-
EQ1
EQ2
EQ3
GND
V
CC2
SDO-
SDO+
N.C.
V
CC
Exposed Pad
FUNCTION
CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be
AC-coupled.
Positive Serial Data Input, CML
Negative Serial Data Input, CML
Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1.
Equalizer Boost Control Logic Input, LVTTL. See Table 1.
Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1.
Supply Ground
CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be
AC-coupled.
Negative Serial Data Output, CML
Positive Serial Data Output, CML
No Connection. Leave unconnected.
+3.3V Core Supply Voltage
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the
Package and Layout Considerations
section).
MAX3804
Detailed Description
General Theory of Operation
The MAX3804’s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).
CML Input and Output Buffers
The MAX3804 input and output CML buffers are termi-
nated with 50Ω to V
CC1
and V
CC2
, respectively. The
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (V
CC
), input (V
CC1
), and output (V
CC2
) circuit-
ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.
Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50Ω termination.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
_______________________________________________________________________________________
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
