DATASHEET
ISL24211
Programmable V
COM
Calibrator with EEPROM and Output Buffer
The ISL24211 is an 8-bit programmable current sink that can
be used in conjunction with an external voltage divider to
generate a voltage source (V
COM
) positioned between the
analog supply voltage and ground. The current sink’s full-scale
range is controlled by an external resistor, R
SET
. With the
appropriate choice of external resistors R
1
and R
2
, the V
COM
voltage range can be controlled between any arbitrary voltage
range. The ISL24211 has an 8-bit data register and 8-bit
EEPROM for storing both a volatile and a permanent value for
its output, with an I
2
C interface to read and write to the
register and EEPROM. After the part is programmed, the I
2
C
interface is no longer needed; on power-up the EEPROM
contents are automatically transferred to the data register, and
the pre-programmed output voltage appears on the
VCOM_OUT pin.
The ISL24211 also features an integrated, wide-bandwidth,
high output drive buffer amplifier that can directly drive the
V
COM
input of an LCD panel.
The ISL24211 is available in an 10 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for
very low profile designs. The ambient operating temperature
range is
-40°C to +85°C
.
FN7585
Rev 0.00
February 23, 2011
Features
• 8-bit, 256-Step, Adjustable Sink Current Output
• 60MHz V
COM
Buffer/Amplifier
• 4.5V to 19.0V Analog Supply Range for Normal Operation
(10.8V Minimum Analog Supply Voltage for Programming)
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• 400kHz, I
2
C Interface
• On-Chip 8-Bit EEPROM
• Guaranteed Monotonic Over-Temperature
• Compatible with applications using the 7-bit ISL45041
• Pb-free (RoHS-compliant)
• Ultra-Thin 10 Ld TDFN (3 x 3 x 0.8mm max)
Applications
• LCD Panel V
COM
Generator
• Electrophoretic Display V
COM
Generator
Related Literature
• AN1627 “ISL24211IRTZ-EVALZ Evaluation Board User
Guide”
Typical Application
3.3V
V
DD
AV
DD
6
3
R
1
7
MICRO-
CONTROLLER
I C
PORT
2
DVR_OUT
SDA
2
8
SCL
1
ISL24211
IN
N
10
WP
VCOM_OUT
R
2
LCD PANEL
I/O PIN
4
V
COM
SET
9
R
SET
5
FIGURE 1. TYPICAL ISL24211 APPLICATION
FN7585 Rev 0.00
February 23, 2011
Page 1 of 12
ISL24211
Block Diagram
V
DD
6
AV
DD
3
SDA
SCL
7
8
I
2
C INTERFACE
DAC
REGISTERS
ANALOG DCP
AND
CURRENT SINK
Q1
A1
8-Bit EEPROM
CS
V
COM
BUFFER
AMPLIFER
2
DVR_OUT
A2
10
VCOM_OUT
WP
4
1
IN
N
9
SET
5
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24211
Pin Configuration
ISL24211
(10 LD TDFN)
TOP VIEW
IN
N
1
DVR_OUT 2
AV
DD
3
WP 4
GND 5
EXPOSED
THERMAL
PAD*
Pin Descriptions
PIN
NAME
IN
N
10 VCOM_OUT
9 SET
8 SCL
7 SDA
6 V
DD
PIN
NUMBER
1
FUNCTION
Negative (inverting) input of the V
COM
buffer op
amp. This pin is used to provide feedback from
the end point of the V
COM
trace.
Adjustable Sink Current Output Pin. The current
sunk into the DVR_OUT pin is equal to the DAC
setting times the maximum adjustable sink
current divided by 256. See the “SET” pin
function description below (pin 9) for the
maximum adjustable sink current setting. Also
tied to the non-inverting input of buffer amp.
Analog Power Supply Input. Bypass to GND
with 0.1µF capacitor.
EEPROM Write Protect. Active Low.
0 = Programming disabled; 1 = Programming
allowed.
Ground connection.
Digital power supply input. Bypass to GND with
0.1µF capacitor.
I
2
C Serial Data Input
I
2
C Clock Input
Maximum Sink Current Adjustment Point.
Connect a resistor from SET to GND to set the
maximum adjustable sink current of the
DVR_OUT pin. The maximum adjustable sink
current is equal to (AV
DD
/20) divided by R
SET
.
Output of the buffer amplifier
Thermal pad should be connected to system
ground plane to optimize thermal performance.
DVR_OUT
2
(*THERMAL PAD CONNECTS TO GND)
AV
DD
WP
3
4
GND
V
DD
SDA
SCL
SET
5
6
7
8
9
VCOM_OUT
PAD
10
-
FN7585 Rev 0.00
February 23, 2011
Page 2 of 12
ISL24211
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL24211IRTZ
ISL24211IRTZ-EVALZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page
ISL24211.
For more information on MSL please see techbrief
TB363.
PART
MARKING
211Z
Evaluation Board
INTERFACE
I
2
C
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 3x3 TDFN
PKG.
DWG. #
L10.3x3A
FN7585 Rev 0.00
February 23, 2011
Page 3 of 12
ISL24211
Absolute Maximum Ratings
Supply Voltage
AV
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET, IN
N
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..V
DD
+ 0.3V
Output Voltage with respect to Ground
DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
DD
Continuous Output Current
DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
10 Ld TDFN Package (Notes 4, 5) . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief
TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5k R
1
= 10k, R
2
= 10k, (See Figure 5), V
COM_OUT
pin
connected to IN
N
, unless otherwise specified. Typicals are at T
A
= +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Electrical Specifications
DC CHARACTERISTICS
V
DD
AV
DD
AV
DD
I
DD
I
AVDD
ZSE
SET
FSE
SET
TCV
SET
V
DVR_OUT
I
DVR_OUT
INL
DNL
V
DD
Supply Range - Operating
AV
DD
Supply Range Supporting EEPROM Programming
AV
DD
Supply Range for Wide-Supply Operation
(not supporting EEPROM Programming)
V
DD
Supply Current
AV
DD
Supply Current
SET Zero-Scale Error
SET Full-Scale Error
SET Voltage Drift
DVR_OUT Voltage Range
Maximum DVR_OUT Sink Current
Integral Non-Linearity
Differential Non-Linearity
I
DVR_OUT
< 0.5mA
V
SET
+ 0.4
4
±2
±1
7
AV
DD
WP = SCL = SDA = V
DD
WP = SCL = SDA = V
DD
2.25
10.8
4.5
95
3.8
3.6
19
19
300
6.5
V
V
V
µA
mA
DVR_OUT CHARACTERISTICS
±3
±8
LSB
LSB
µV/°C
V
mA
LSB
LSB
OUTPUT AMPLIFIER CHARACTERISTICS
V
OS
TCV
OS
I
B
CMRR
PSRR
A
VOL
V
OL
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Open Loop Gain
Output Swing Low
I
L
= -5mA
55
60
55
±2
-6.3
0.001
75
82
75
50
150
±1
±15
mV
µV/°C
µA
dB
dB
dB
mV
FN7585 Rev 0.00
February 23, 2011
Page 4 of 12
ISL24211
Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5k R
1
= 10k, R
2
= 10k, (See Figure 5), V
COM_OUT
pin
connected to IN
N
, unless otherwise specified. Typicals are at T
A
= +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
(Continued)
SYMBOL
V
OH
I
SC
SR
Output Swing High
Short Circuit Current (Sinking)
Short Circuit Current (Sourcing)
Slew Rate (Rising)
Slew Rate (Falling)
t
S
BW
Settling Time to 0.2%
-3dB Bandwidth
1k || 8pF Load
1k || 8pF Load
PARAMETER
TEST CONDITIONS
I
L
= 5mA
MIN
(Note 6)
17.85
300
450
70
50
TYP
17.9
430
555
116
93
150
60
MAX
(Note 6)
UNITS
V
mA
mA
V/µs
V/µs
ns
MHz
Electrical Specifications
I
2
C INPUTS AND OUTPUT
V
IH_I2C
V
IL_I2C
V
HYS_I2C
I
L_I2C
V
OL_I2C
V
IH_WP
V
IL_WP
V
HYS_WP
I
L_WP
SDA, SCL Logic 1 Input Voltage
SDA, SCL Logic 0 Input Voltage
SDA, SCL Hysteresis
SDA, SCL Input Leakage Current
SDA Output Logic Low
WP Input Logic High
WP Input Logic Low
WP Input Hysteresis
WP Input Leakage Current
I
2
C Clock Frequency
I
2
C Clock High Time
I
2
C Clock Low Time
I
2
C Spike Rejection Filter Pulse Width
I
2
C Data Set Up Time
I
2
C Data Hold Time
I
2
C Time Between Stop and Start
I
2
C Repeated Start Condition Set-up
I
2
C Repeated Start Condition Hold
I
2
C Stop Condition Set-up
SDA Pin Capacitance
SCL Pin Capacitance
EEPROM Write Cycle Time
0.6
1.3
0
250
250
200
0.6
0.6
0.6
10
10
100
50
-0.20
260
-0.5
-1
I = -3mA
0.7V
DD
0.3V
DD
260
±1
0.4
1.44
0.55
V
V
mV
µA
V
V
V
mV
µA
I
2
C TIMING
f
CLK
t
SCH
t
SCL
t
DSP
t
SDS
t
SDH
t
BUF
t
STS
t
STH
t
SPS
C
SDA
C
SCL
t
WR
400
kHz
µs
µs
ns
ns
ns
µs
µs
µs
µs
pF
pF
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7585 Rev 0.00
February 23, 2011
Page 5 of 12
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