HIGH-SPEED 3.3V
64/32K x 8 SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
◆
IDT70V9089/79S/L
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT70V9089/79S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9089/79L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
◆
◆
◆
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
,
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
- I/O
7R
A
15L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3750 drw 01
NOTE:
1. A
15
X
is a NC for IDT70V9079.
JULY 2014
1
©2014 Integrated Device Technology, Inc.
DSC 3750/12
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The IDT70V9089/79 is a high-speed 64/32K x 8 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
Description:
With an input data register, the IDT70V9089/79 has been opti-
mized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by
CE
0
and
CE
1,
permits the on-chip circuitry of each port to enter a very low
standby power mode. Fabricated using CMOS high-performance
technology, these devices typically operate on only 429mW of
power.
Pin Configurations
(2,3,4)
NC
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
V
SS
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
70
6
69
7
68
8
67
9
66
10
IDT70V9089/79PF
65
11
PN100
(5)
64
12
100-PIN TQFP
63
13
TOP VIEW
(6)
62
14
61
15
60
16
59
17
58
18
57
19
56
20
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10/30/13
Index
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
(1)
NC
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
FT/PIPE
L
NC
NC
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
(1)
NC
V
SS
NC
NC
NC
NC
CE
0R
CE
1R
CNTRST
R
R/W
R
OE
R
FT/PIPE
R
V
SS
NC
3750 drw 02
NOTES:
1. A
15X
is a NC for IDT70V9079.
2. All Vcc pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
GND
NC
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
IL
I/O
0L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
NC
NC
NC
2
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
15L
(1)
I/O
0L
- I/O
7L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
FT/PIPE
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
15R
(1)
I/O
0R
- I/O
7R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
FT/PIPE
R
V
DD
V
SS
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
3750 tbl 01
NOTE:
1. A
15X
is a NC for IDT70V9079.
2.
LB
and
UB
are single buffered regardless of state of
FT/PIPE.
3.
CEo
and CE
1
are single buffered when
FT/PIPE
= V
IL
,
CEo
and CE
1
are double buffered when
FT/PIPE
= V
IH
,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and
Enable Control
(1,2,3)
OE
X
X
X
L
H
CLK
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
CE
1
X
L
H
H
H
R/
W
X
X
L
H
X
I/O
0-7
High-Z
High-Z
DATA
IN
DATA
OUT
High-Z
Mode
Deselected - Power Down
Deselected - Power Down
Write
Read
Outputs Disabled
3750 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
Truth Table II—Address Counter Control
(1,2,3)
External
Address
An
X
X
X
Previous
Internal
Address
X
An
An + 1
X
Internal
Address
Used
An
An + 1
An + 1
A
0
CLK
↑
↑
↑
↑
ADS
L
(4)
H
H
X
CNTEN
X
L
(5)
H
X
CNTRST
H
H
H
L
(4)
I/O
(3)
D
I/O
(n)
D
I/O
(n+1)
D
I/O
(n+1)
D
I/O
(0)
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Reset to Address 0
3750 tbl 03
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
CNTRST
are independent of all other signals including
CE
0
and CE
1
.
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6.42
3
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
3750 tbl 04
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.2
-0.3
(2)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+ 0.3V
(1)
0.8
Unit
V
V
V
V
3750 tbl 05
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. V
TERM
must not exceed V
DD
+0.3V.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Capacitance
(T
A
= +25°C, f = 1.0MH
z
)
Unit
V
Symbol
C
IN
C
OUT
(3)
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3750 tbl 07
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
T
BIAS
T
STG
T
JN
I
OUT
-55 to +125
-65 to +150
+150
50
o
C
C
C
o
o
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
mA
3750 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
3. Ambient Temperature Under Bias. Chip Deselected.
4
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V9089/79S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
DD
= 3.3V, V
IN
= 0V t
o
V
DD
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V t
o
V
DD
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70V9089/79L
Min.
___
___
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3750 tbl 08
2.4
2.4
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(6)
(V
DD
= 3.3V ± 0.3V)
70V9089/79X6
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
L
and
CE
R
= V
IL
Outputs Disabled
f = f
MAX
(1)
Version
COM'L
IND
COM'L
IND
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs Disabled,
f=f
MAX
(1)
Both Ports
CE
R
and
CE
L
> V
DD
- 0.2V
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Disabled, f = f
MAX
(1)
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(4)
220
220
____
____
70V9089/79X7
Com'l Only
Typ.
(4)
200
200
____
____
70V9089/79X9
Com'l Only
Typ.
(4)
180
180
____
____
Max.
395
350
____
____
Max.
335
290
____
____
Max.
260
225
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(1)
70
70
____
____
145
130
____
____
60
60
____
____
115
100
____
____
50
50
____
____
75
65
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
150
150
____
____
280
250
____
____
130
130
____
____
240
210
____
____
110
110
____
____
170
150
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
1.0
0.4
____
____
5
3
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
140
140
____
____
270
240
____
____
120
120
____
____
230
200
____
____
100
100
____
____
160
140
____
____
mA
3750 tbl 09a
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD
= 3.3V, TA = 25°C for Typ, and are not production tested. I
CC DC
(f=0) = 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
DD
- 0.2V
CE
X
> V
DD
- 0.2V means
CE
0X
> V
DD
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.42
5
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