DATASHEET
Triple Analog Video Delay Lines
ISL59920, ISL59921, ISL59922, ISL59923
The ISL59920, ISL59921, ISL59922, and ISL59923 are triple
Features
analog delay lines that provide skew compensation between
three high-speed signals. These parts are ideal for
compensating for the skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable (with differing electrical lengths on each
twisted pair) when transmitting analog video.
Using a simple serial interface, the ISL59920, ISL59921,
ISL59922, and ISL59923’s delays are programmable in steps
of 2, 1.5, 1, or 2ns (respectively) for up to a total delay of 62,
46.5, 31, or 30ns (respectively) on each channel. The gain of
the video amplifiers can be set to x1 (0dB) or x2 (6dB) for
back-termination. The delay lines require a ±5V supply.
• 30, 31, 46.5, or 62ns Total delay
• 1.0, 1.5, or 2.0ns Delay step increments
• Very low offset voltage
• Drop-in compatible with the EL9115
• Low power consumption
• 20 Ld QFN package
• Pb-Free (RoHS compliant)
Applications
• Skew control for RGB video signals
• Generating programmable high-speed analog delays
1
V
SP
19
TESTR
17
TESTB
18
TESTG
16
V
SPO
CENABLE 7
2
R
IN
+
DELAY LINE
+
R
OUT
15
4
G
IN
+
DELAY LINE
+
G
OUT
13
6
B
IN
+
DELAY LINE
+
B
OUT
11
X2 20
CONTROL LOGIC
V
SMO
12
9
10
8
SDATA
SCLOCK
SENABLE
GND
V
SM
[BOTTOM PLATE]
C
3
5
14
FIGURE 1. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
September 25, 2014
FN6826.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas LLC 2009, 2010, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
GND
ISL59920, ISL59921, ISL59922, ISL59923
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL59920IRZ
ISL59921IR
ISL59922IRZ
ISL59923IRZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information pages for
ISL59920, ISL59921, ISL59922, ISL59923.
For more information on
MSL, please see tech brief
TB363
PART
MARKING
59920 IRZ
59921 IRZ
59922 IRZ
59923 IRZ
MAX
DELAY
(ns)
62
46.5
31
30
DELAY STEP
SIZE (ns)
2.0
1.5
1.0
2.0
TYPICAL POWER
DISSIPATION
(mW)
645
645
645
540
PACKAGE
(Pb-free)
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
PKG.
DWG. #
L20.5x5C
L20.5x5C
L20.5x5C
L20.5x5C
Pin Configuration
ISL59920, ISL59921, ISL59922, ISL59923
(20 LD 5x5 QFN)
TOP VIEW
18 TESTG
19 TESTR
17 TESTB
16 V
SPO
15 R
OUT
14 GNDO
THERMAL
PAD
13 G
OUT
12 V
SMO
11 B
OUT
CENABLE 7
SENABLE 8
SCLOCK 10
B
IN
6
SDATA 9
20 X2
V
SP
1
R
IN
2
GND 3
G
IN
4
V
SM
5
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
PIN NAME
V
SP
R
IN
GND
G
IN
V
SM
B
IN
CENABLE
+5V for delay circuitry and input amp
Red channel video input
0V for delay circuitry supply
Green channel video input
-5V for input amp
Blue channel video input
Chip Enable input, active high: logical high enables chip, low disables chip. This pin should be low
at power-on until at least 30ms after the power supply has settled to within 5% of its final value.
For more information, see
“CENABLE at Power-On” on page 16.
Serial Enable input, active low: logical low enables serial communication
Serial Data input, logic threshold 1.2V: data to be programmed into chip
Serial Clock input: Clock to enter data; logical; data written on negative edge
Blue channel video output
PIN DESCRIPTION
8
9
10
11
SENABLE
SDATA
SCLOCK
B
OUT
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FN6826.3
September 25, 2014
ISL59920, ISL59921, ISL59922, ISL59923
Pin Descriptions
(Continued)
PIN NUMBER
12
13
14
15
16
17
18
19
20
Thermal Pad
PIN NAME
V
SMO
G
OUT
GNDO
R
OUT
V
SPO
TESTB
TESTG
TESTR
X2
-5V for video output buffers
Green channel video output
0V reference for input and output buffers
Red channel video output
+5V for video output buffers
Blue channel phase detector output
Green channel phase detector output
Red channel phase detector output
Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
MUST be tied to -5V. For best thermal conductivity, tie to a larger -5V copper plane (inner or
bottom). Use many vias to minimize thermal resistance between thermal pad and copper plane.
Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND planes
together.
PIN DESCRIPTION
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FN6826.3
September 25, 2014
ISL59920, ISL59921, ISL59922, ISL59923
Absolute Maximum Ratings
(T
A
= +25°C)
Supply Voltage (V
S
+ to V
S
-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
20 Lead QFN (Notes
4, 5)
. . . . . . . . . . . . . .
31
2
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379
5. For
JC,
the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
d
t
V
SP
= V
SPO
= +5V, V
SM
= V
SMP
= -5V, GAIN = 2, T
A
= +25°C, exposed die plate = -5V, x2 = 5V, R
LOAD
= 150Ω
on all video outputs, unless otherwise specified.
DESCRIPTION
Nominal Delay Increment (Note
7)
ISL59920
ISL59921
ISL59922
ISL59923
t
MAX
Maximum Delay
ISL59920
ISL59921
ISL59922
ISL59923
D
ELDT
t
PD
Delay Difference Between Channels for Same
Delay Settings On All Channels
Propagation Delay
ISL59920, ISL59923, measured input to
output, delay setting = 0ns
ISL59921, measured input to output, delay
setting = 0ns
ISL59922, measured input to output, delay
setting = 0ns
BW -3dB
3dB Bandwidth, 0ns Delay Time
ISL59920, ISL59923
ISL59921
ISL59922
BW ±0.1dB
±0.1dB Bandwidth, 0ns Delay Time
ISL59920, ISL59923
ISL59921
ISL59922
SR
Slew Rate
ISL59920, 20 to 80, delay = 0ns
ISL59921, 20 to 80, delay = 0ns
ISL59922, 20 to 80, delay = 0ns
ISL59923; 20 to 80, delay = 0ns
TEST CONDITIONS
MIN
(Note
6)
1.8
1.4
0.9
1.8
55
42.5
26.5
26.5
TYP
2
1.5
1
2
62
46.5
31
30
1
10
8
7
153
200
230
50
60
50
550
640
700
550
MAX
(Note
6)
2.2
1.7
1.2
2.3
68
53.5
38.5
34.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
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FN6826.3
September 25, 2014
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
PARAMETER
t
R
- t
F
V
SP
= V
SPO
= +5V, V
SM
= V
SMP
= -5V, GAIN = 2, T
A
= +25°C, exposed die plate = -5V, x2 = 5V, R
LOAD
= 150Ω
on all video outputs, unless otherwise specified. (Continued)
DESCRIPTION
Transient Response Time
TEST CONDITIONS
ISL59920, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59921, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59922, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59923, 20% to 80%, for any delay, 1V step
delay = 0ns
V
OVER
Settling Time
THD
X
Voltage Overshoot
Output Settling after Delay Change / Offset
Calibration
Total Harmonic Distortion
Crosstalk
For any delay, response to 1V step input
Output settling time from rising edge of
SENABLE
1V
P-P
10MHz sinewave, offset by +0.2V at mid
delay setting
Stimulate G, measure R/B at 1MHz,
ISL59920, ISL59921, ISL59923
ISL59922
V
N
G_0
G_m
G_f
DG_m0
DG_f0
DG_fm
V
IN
Output Noise
Gain Zero Delay
Gain Mid Delay
Gain Full Delay
Difference in Gain, 0 to Mid
Difference in Gain, 0 to Full
Difference in Gain, Mid to Full
Input Voltage Range
ISL59920, Gain remains > 90% of nominal,
Gain = 2
ISL59921, Gain remains > 90% of nominal,
Gain = 2
ISL59922, Gain remains > 90% of nominal,
Gain = 2
ISL59923, Gain remains > 90% of nominal,
Gain = 2
I
B
R
IN
, G
IN
, B
IN
Input Bias Current
ISL59920, ISL59921
ISL59922, ISL59923
V
OS
Z
OUT
Output Offset Voltage
Output Impedance
Post offset calibration (Note
9),
Delay = 0ns
and Delay = Full
ISL59920, ISL59921, Enabled,
Chip enable = 5V
ISL59922, ISL59923, Enabled,
Chip enable = 5V
Disabled, Chip enable = 0V
+PSRR
-PSRR
I
OUT
V
IH
V
IL
Rejection of Positive Supply
Rejection of Negative Supply
Output Drive Current
Logic High
Logic Low
10Ω load, 0.5V drive
Switch high threshold
Switch low threshold
0.8
43
Bandwidth = 150MHz
1.74
1.67
1.6
-8
-12
-10
-0.7
-0.7
-0.7
-0.7
3
1.5
-25
4.5
3.5
8
-42
-58
53
-29
-46
70
1.6
-4
5.4
6
MIN
(Note
6)
TYP
1.7
1.6
1.43
1.7
4
3
-43
-80
-78
2
1.8
1.8
1.8
0.6
-1.8
-1.7
1.92
1.97
2
7.5
10
7.5
1.1
1.04
1.04
1.15
8
8
+20
6.3
6.3
-38
-63
-59
MAX
(Note
6)
UNITS
ns
ns
ns
ns
%
µs
dB
dB
dB
mV
RMS
V/V
V/V
V/V
%
%
%
V
V
V
V
µA
µA
mV
Ω
Ω
MΩ
dB
dB
mA
V
V
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FN6826.3
September 25, 2014
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