19-3741; Rev 1; 8/10
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
General Description
The MAX1434/MAX1436/MAX1437/MAX1438 evaluation
kits (EV kits) are fully assembled and tested circuit
boards that contain all the components necessary to
evaluate the performance of this family of octal 10-/12-
bit analog-to-digital converters (ADCs). These ADCs
accept differential analog input signals. The EV kits
generate these signals from user-provided single-
ended input sources. The EV kits’ digital outputs can be
easily sampled with a user-provided high-speed logic
analyzer or data-acquisition system. The EV kits also
feature an on-board deserializer to simplify integration
with standard logic analysis systems. The EV kits oper-
ate from 1.8V and 3.3V (plus 1.5V if the FPGA is used)
power supplies and include circuitry that generates a
clock signal from an AC signal provided by the user.
Features
o
Low-Voltage and Low-Power Operation
o
Optional On-Board Clock-Shaping Circuitry
o
Serial Scalable Low-Voltage Signaling
(SLVS)/Low-Voltage Differential Signaling (LVDS)
Outputs
o
On-Board LVPECL Differential Output Drivers
o
On-Board Deserializer
o
LVDS Test Mode
o
Fully Assembled and Tested
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Part Selection Table
PART NUMBER
MAX1434ECQ+D
MAX1436ECQ+D
MAX1437ECQ+D
MAX1438ECQ+D
BITS
10
12
12
12
SPEED (Msps)
50
40
50
65
PART
MAX1434EVKIT
MAX1436EVKIT
MAX1437EVKIT
MAX1438EVKIT
Ordering Information
TYPE
EV Kit
EV Kit
EV Kit
EV Kit
+Denotes
lead(Pb)-free and RoHS compliant.
D = Dry Pack.
Component List
DESIGNATION QTY
C1–C8, C10,
C11, C12,
C57–C64,
C81–C85,
C139, C140,
C147–C156
C9, C29–C44,
C56, C77, C78,
C80, C92, C93,
C134–C137,
C146
C13–C20,
C65–C72
C21–C28,
C126–C133
DESCRIPTION
DESIGNATION QTY
C45, C46, C47,
C86–C89, C143
C48, C49, C50,
C144
C51, C52, C53,
C90, C91, C145
8
DESCRIPTION
220µF ±20%, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006R0250
Not installed, capacitors (C-case)
10µF ±10%, 10V X5R ceramic
capacitors (1210)
TDK C3225X5R1A106K
2.2µF ±20%, 6.3V X5R ceramic
capacitor (0603)
TDK C1608X5R0J225M
0.01µF ±10%, 25V X7R ceramic
capacitors (0402)
TDK C1005X7R1E103K
Not installed, ceramic capacitors
(0402)
36
0.1µF ±10%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104K
0
6
28
1.0µF ±10%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105K
Not installed, ceramic capacitors
(0603)
39pF ±5%, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H390J
C54
1
0
C55,
C157–C176
C73–C76,
C122–C125
21
16
0
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Component List (continued)
DESIGNATION QTY
C79, C138,
C142
3
DESCRIPTION
10µF ±10%, 4V X5R ceramic
capacitors (0603)
TDK C1608X5R0G106K
0.1µF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
100µF ±20%, 6.3V X5R ceramic
capacitor (1210)
TDK C3225X5R0J107M
Dual Schottky diode (SOT23)
Central Semi CMPD6263S or
Diodes Inc. BAS70-04
Green surface-mount LEDs (0603)
SMA PC-mount vertical connectors
2-pin headers
Dual-row, 40-pin (2 x 20) headers
9-pin header
3-pin headers
Dual-row, 8-pin (2 x 4) header
Digital logic n-channel MOSFET
(SOT23)
Central Semi 2N7002
Not installed, resistors (0603)
U4
0
Not installed, resistors (0402)
U5
9
30
49.9Ω ±1% resistors (0603)
49.9Ω ±1% resistors (0402)
1
1
U2
1
DESIGNATION QTY
R45–R50,
R100–R103
R51
R52, R53, R56
R54
R55
R57
R94, R95
R96, R97
R99
R104
SW1
T1–T8
TP1–TP8, TP13,
TP14, TP15
TP9–TP12
TP16
U1
1
1
10
1
3
1
1
1
2
2
1
1
1
8
0
4
1
1
DESCRIPTION
100Ω ±1% resistors (0603)
100kΩ potentiometer, 19-turn, 3/8in
4.02kΩ ±1% resistors (0603)
5kΩ potentiometer, 19-turn, 3/8in
2kΩ ±1% resistor (0603)
13.0kΩ ±1% resistor (0603)
4.7kΩ ±5% resistors (0603)
330Ω ±5% resistors (1206)
162Ω ±1% resistor (0603)
10kΩ ±5% resistor (0603)
Momentary contact switch
1:1 800MHz RF transformers
Mini-Circuits ADT1-1WT
Test points, not installed
PC test points (red)
PC test point (black)
See EV kit specific component list
Single LVDS line receivers (8 SO)
Maxim MAX9111ESA
Low-noise, low-distortion op amp
(5 SOT23)
Maxim MAX4250EUK
TinyLogic UHS dual inverter
(6 SC70)
Fairchild NC7WZ04P6X
Virtex II platform FPGA (256 FGBGA)
Xilinx XC2V80-5FG256C or
Xilinx XC2V80-5FG256I
PROM (SO-20)
Xilinx XC18V01SO20C
LVDS/anything-to-LVPECL translators
(8 µMAX
®
)
Maxim MAX9375EUA
Shunts (JU1–JU14)
PCB: MAX1434/6/7/8 EVALUATION
KIT
C94–C121
28
C141
1
D1
D2, D3
IN0–IN7,
CLOCK
J1–J8, JU14
J9–J13, J15
J14
JU1–JU11,
JU13
JU12
N1
R1–R8,
R22–R25,
R62–R73
R9–R16,
R26–R35,
R77–R81,
R87–R93, R98
R17–R21,
R58–R61
R36,
R105–R133
R37–R44, R74,
R75, R76,
R82–R86
1
2
9
9
6
1
12
U3
1
0
U6
1
U7–U16
None
None
10
14
1
16
10Ω ±1% resistors (0805)
µMAX is a registered trademark of Maxim Integrated Products, Inc.
2
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
EV Kit Component List
EV KIT PART NUMBER
MAX1434EVKIT
MAX1436EVKIT
MAX1437EVKIT
MAX1438EVKIT
U1
DESIGNATION
DESCRIPTION
MAX1434ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1436ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1437ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1438ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
Component Suppliers
SUPPLIER
AVX Corporation
Central Semiconductor Corp.
Diodes Incorporated
Fairchild Semiconductor Corp.
Mini-Circuits
TDK Corp.
PHONE
843-946-0238
631-435-1110
805-446-4800
888-522-5372
718-934-4500
847-803-6100
WEBSITE
www.avxcorp.com
www.centralsemi.com
www.diodes.com
www.fairchildsemi..com
www.minicircuits.com
www.component.tdk.com
Note:
Indicate that you are using the MAX1434, MAX1436, MAX1437, or MAX1438 when contacting these component suppliers.
Quick Start
Recommended Equipment
•
DC power supplies:
Clock (CVDD) 3.3V, 100mA
Analog (AVDD) 1.8V, 500mA
Digital (OVDD) 1.8V, 150mA
Optional
Buffers (VPECL) 3.3V, 400mA
Deserializer Core (VD1.5) 1.5V, 200mA
•
•
•
•
•
Deserializer I/O (VD3.3) 3.3V, 200mA
Signal generator with low phase noise and low jitter
for clock input signal (e.g., HP 8662A, HP 8644B)
Signal generator for analog signal inputs (e.g., HP
8662A, HP 8644B)
Logic analyzer or data-acquisition system (e.g., HP
16500C, TLA715)
Analog bandpass filters (e.g., Allen Avionics, K&L
Microwave) for input signal and clock signal
Digital voltmeter
Procedure
The EV kit is a fully assembled and tested surface-
mount board. Follow the steps below to verify board
operation.
Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed in the following
locations:
JU1 (pins 2-3)
→
single termination
JU2 (pins 2-3)
→
LVDS outputs
JU3 (pins 2-3)
→
normal operation
JU4 (pins 2-3)
→
ADC enabled
JU7 (pins 2-3)
→
two’s-complement output
JU8 (pins 2-3)
→
FPGA enabled
JU9, JU10, JU11 (pins 2-3)
→
channels 0–3
output from FPGA
JU12 (pins 3-4)
→
internal reference enabled
JU14 (not installed)
→
disconnect external ref-
erence buffer
2) Verify that shunts are installed in the following
locations for configuring the specific EV kit:
a)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→
39MHz to 50MHz clock frequency range for
the MAX1434 EV kit.
_______________________________________________________________________________________
3
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
b)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→
32.5MHz to 40MHz clock frequency range for
the MAX1436 EV kit.
JU5, JU6, JU13 (pins 2-3)
→
45MHz to 50MHz
clock frequency range for the MAX1437 EV kit.
JU5, JU6, JU13 (pins 2-3)
→
45MHz to 65MHz
clock frequency range for the MAX1438 EV kit.
frequency with an amplitude
≤1.4V
P-P
. All signal
generators should be phase-locked.
19) Verify that the PROGRAMMING LED (D2) is off.
20) Momentarily press switch SW1 and verify that the
LOCKED LED (D3) is on.
21) Enable the logic analyzer.
22) Collect data using the logic analyzer.
c)
d)
3) Connect the clock signal generator to the input of
the clock bandpass filter.
4) Connect the output of the clock bandpass filter to
the clock SMA connector.
5) Connect the analog input signal generator to the
input of the analog bandpass filter.
6) Connect the output of the analog bandpass filter to
either one of the SMA connectors labeled IN0–IN7.
The analog input signals can also be monitored at
the 2-pin headers J1–J8.
Note:
All eight channels can be operated indepen-
dently or simultaneously.
7) Connect the logic analyzer to either header J9
(SLVS- or LVDS-compatible signals) or J10–J13
(deserialized 3.3V CMOS-compatible signals). See
the
Output Bit Locations
section in this document
for header connections.
8) Connect the 1.8V, 500mA power supply to AVDD.
Connect the ground terminal of this supply to GND.
9) Connect the 1.8V, 150mA power supply to OVDD.
Connect the ground terminal of this supply to GND.
10) Connect the 3.3V, 100mA power supply to CVDD.
Connect the ground terminal of this supply to GND.
11) Connect the 3.3V, 400mA power supply to VPECL.
Connect the ground terminal of this supply to GND.
12) Connect the 1.5V, 200mA power supply to VD1_5.
Connect the ground terminal of this supply to GND.
13) Connect the 3.3V, 200mA power supply to VD3_3.
Connect the ground terminal of this supply to GND.
14) Turn on the VD3_3 power supply.
15) Turn on the VD1_5 power supply.
16) Verify that the PROGRAMMING LED (D2) and the
LOCKED LED (D3) are off.
17) Turn on the remaining power supplies.
18) Enable the signal generators. Set the clock signal
generator to output
as specified to configuration
signal, with a 2.6V
P-P
amplitude or higher. Set the
analog input signal generators to output the desired
Detailed Description of Hardware
The EV kit is a fully assembled and tested circuit board
that contains all the components necessary to evaluate
the performance of the MAX1438, MAX1437, MAX1436,
or MAX1434.
The ADCs accept differential input signals; however,
on-board transformers (T1–T8) convert the single-
ended signals applied to the IN0–IN7 SMA connectors,
to the required differential signal. The input signals of
the ADC can be measured using a differential oscillo-
scope probe at headers J1–J8.
Output level translators (U7–U16) buffer and convert
the SLVS or LVDS output signals of the ADC to higher
voltage LVPECL signals, which can be captured by a
wide variety of logic analyzers. The SLVS/LVDS output
signals are accessible at header J9 and the LVPECL
output signals are accessible at header J15.
The EV kit PC board is designed as a six-layer board to
optimize performance of the ADC. Separate analog,
digital, clock, and buffer power planes minimize noise
coupling between analog and digital signals. 50Ω
coplanar transmission lines are used for analog and
clock inputs. 100Ω differential coplanar transmission
lines are used for all digital LVDS outputs. All differential
outputs are terminated with 100Ω termination resistors
between the true and complementary digital outputs.
The trace lengths of the 100Ω differential SLVS/LVDS
lines are matched to within a few thousands of an inch
to minimize layout-dependent data skew.
Power Supplies
For best performance, the EV kit requires separate ana-
log, digital, clock, and buffer power supplies. Two 1.8V
power supplies are used to power the analog (AVDD)
and digital (OVDD) portion of the ADC. The clock cir-
cuitry (CVDD) is powered by a 3.3V power supply. A
separate 3.3V power supply (VPECL) is used to power
the output buffers (U7–U16) of the EV kit. 1.5V (VD1_5)
and 3.3V (VD3_3) power supplies are required to power
the deserializer circuit.
4
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Power-Down
Jumper JU4 controls the power-management feature of
data converter U1. See Table 1 for jumper JU4 shunt
positions.
Evaluate: MAX1434/MAX1436/MAX1437/MAX1438
Table 2. MAX1434 PLL Jumper Settings
(JU5, JU6, JU13)
JUMPER
JU13
(PLL1)
2-3
SHUNT POSITION
2-3*
2-3
2-3
1-2
1-2
1-2
1-2
JU6
(PLL2)
2-3
2-3*
1-2
1-2
2-3
2-3
1-2
1-2
JU5
(PLL3)
2-3
1-2*
2-3
1-2
2-3
1-2
2-3
1-2
39.0
27.0
19.5
13.5
9.8
6.8
4.8
CLOCK INPUT RANGE
(MHz)
MIN
Unused
50.0
39.0
27.0
19.5
13.5
9.8
6.8
MAX
Table 1. Power-Down Jumper Settings (JU4)
SHUNT
POSITION
1-2
2-3*
POWER-DOWN
CONNECTIONS
AVDD
GND
EV KIT FUNCTION
ADC disabled
ADC enabled
*Default
configuration: JU4 (2-3).
Clock
By default, the user-provided AC-coupled clock signal
applied to the EV kit CLOCK SMA connector is buffered
on board with two inverters (U4). In this mode, diode
D1 limits the amplitude of the clock signal. Overdriving
the clock input can increase the slew rate of the differ-
ential signal, thereby reducing clock jitter. The frequen-
cy of the signal should not exceed the maximum
sampling rate of the ADC. The sinusoidal input signal
frequency (f
CLK
) determines the sampling rate of the
ADC. The clock signal applied to the ADC can be
observed at test point TP10.
*Default
configuration: JU5, JU6 (2-3), JU13 (1-2).
Table 3. MAX1436 PLL Jumper Settings
(JU5, JU6, JU13)
JUMPER
JU13
(PLL1)
2-3
SHUNT POSITION
2-3*
2-3
2-3
1-2
1-2
1-2
1-2
JU6
(PLL2)
2-3
2-3*
1-2
1-2
2-3
2-3
1-2
1-2
JU5
(PLL3)
2-3
1-2*
2-3
1-2
2-3
1-2
2-3
1-2
32.5
22.5
16.3
11.3
8.1
5.6
4.0
CLOCK INPUT RANGE
(MHz)
MIN
Unused
40.0
32.5
22.5
16.3
11.3
8.1
5.6
MAX
Optional Clock-Shaping Circuit
The EV kit also features an optional on-board clock-
shaping circuit that generates a clock signal with vari-
able duty cycle from the AC-coupled sine-wave signal
applied to the CLOCK SMA connector. The MAX9111
differential line receiver (U2) processes the clock input
signal and generates the required CMOS clock signal.
To use this circuitry, cut the trace on the printed circuit
(PC) board at R78 and install 0Ω resistors at R35 and
R77. The signal’s duty cycle can be adjusted with poten-
tiometer R54. With a 3.3V clock supply voltage (CVDD),
a clock signal with a 50% duty cycle (recommended)
can be achieved by adjusting R54 until a voltage of
1.32V is produced across test points TP12 and TP16.
PLL Frequency Mode Selection
When driving the EV kit with clock signals lower than
the maximum specified sampling rate of the ADC, the
phased-locked-loop (PLL) circuit of the ADC must be
set accordingly. Refer to the PLL Inputs (PLL0–PLL3)
section in the ADC data sheet for further details about
the operation of the internal PLL. Jumpers JU5, JU6,
and JU13 control the PLL mode of the ADC. See Tables
2, 3, 4, or 5 for shunt positions. Configure jumpers JU5,
JU6, and JU13 accordingly and ensure that the clock
signal frequency falls between the minimum and maxi-
mum limits listed in Table 2 through Table 5.
*Default
configuration: JU5, JU6 (2-3), JU13 (1-2).
_______________________________________________________________________________________________________
5
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