Datasheet
Serial EEPROM Series Standard EEPROM
WLCSP EEPROM
BU9897GUL-W
(128Kbit)
●General
Description
BU9897GUL-W is a serial EEPROM of I
2
C BUS interface method.
Memory density is 128Kbit (16,384×8bit) , compact package VCSP50L2.
●Features
Completely conforming to the world standard I
2
C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
Other devices than EEPROM can be connected to the same port, saving microcontroller port.
1.7V to 5.5V single power source action most suitable for battery use.
FAST MODE :400kHz at 1.7V to 5.5V
Page write mode useful for initial value write at factory shipment.
Auto erase and auto end function at data rewrite.
Low current consumption
At write operation (5.0V)
: 0.5mA (Typ.)
At read operation (5.0V)
: 0.2mA (Typ.)
At standby operation (5.0V)
: 0.1µA (Typ.)
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
Compact package
W(Typ.) x D(Typ.) x H(Max.)
: 2.44mm x 1.99mm x 0.55mm
Data rewrite up to 1,000,000 times
Data kept for 40 years
Noise filter built in SCL / SDA terminal
Shipment data all address FFh
●Page
write
Product number
BU9897GUL-W
Number of pages
64Byte
●Absolute
Maximum Ratings
(Ta=25℃)
Parameter
symbol
Impressed voltage
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
V
CC
Pd
Tstg
Topr
－
Ratings
-0.3 to 6.5
220
-65 to 125
-40 to 85
-0.3 to V
CC
+1.0
Unit
V
mW
℃
℃
V
Remarks
When using at Ta=25℃or higher, 2.2mW to be reduced per 1℃
The Max value of Terminal Voltage is not over 6.5V.
●Memory
cell characteristics
(Ta=25℃, V
CC
=1.7V to 5.5V)
Limits
Parameter
Min.
Typ.
Number of data rewrite times
*1
Data hold years
*1
Max.
－
－
Unit
Times
Years
1,000,000
40
－
－
*1 Not 100% TESTED
●Recommended
Operating Ratings
Parameter
Power source voltage
Input voltage
Symbol
V
CC
V
IN
Ratings
1.7 to 5.5
0 to V
CC
Unit
V
○Product
structure：Silicon monolithic integrated circuit
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111½14½001
○This
product is not designed protection against radioactive rays
1/22
TSZ02201-0R2R0G100500-1-2
21.Dec.2017 Rev.002
BU9897GUL-W (128Kbit)
●Electrical
Characteristics
(Unless otherwise specified Ta=-40℃ to 85℃, V
CC
=1.7V to 5.5V)
Limits
Parameter
Symbol
Unit
Min
Typ.
Max.
"H" Input Voltage1
"L" Input Voltage1
"L" Output Voltage1
"L" Output Voltage2
Input Leakage Current
Output Leakage Current
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
I
CC1
Current consumption
at action
I
CC2
I
SB
0.7V
CC
－0.3
－
－
－1
－1
－
－
－
－
－
－
－
－
－
－
－
－
V
CC
+1.0
0.3V
CC
0.4
0.2
1
1
2.5
0.5
2.0
V
V
V
V
µA
µA
mA
mA
µA
I
OL
=3.0mA,
I
OL
=0.7mA,
2.5V≦V
CC
≦5.5V(SDA)
1.7V≦V
CC
＜2.5V(SDA)
Condition
V
IN
=0V to V
CC
V
OUT
=0V to V
CC
(SDA)
V
CC
=5.5V , f
SCL
=400kHz, tWR=5ms
Byte Write, Page Write
V
CC
=5.5V , f
SCL
=400kHz
Random read, Current read,
Sequential read
V
CC
=5.5V , SDA・SCL=V
CC
, WP=GND
Standby Current
●Action
timing characteristics
(Unless otherwise specified Ta=-40℃ to 85℃½V
CC
=1.7V to 5.5V)
Limits
Parameter
Symbol
Min.
Typ.
SCL Frequency
Data clock "High" time
Data clock "Low" time
SDA, SCL rise time
SDA, SCL fall time
*1
*1
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
0
0.1
1.0
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
400
－
－
0.3
0.3
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
ns
µs
µs
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition data setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA,SCL terminal)
WP hold time
WP setup time
WP valid time
*1 : Not 100% TESTED
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
2/22
TSZ02201-0R2R0G100500-1-2
21.Dec.2017 Rev.002
BU9897GUL-W (128Kbit)
●Sync
Data Input / Output Timing
tR
SCL
tHD :STA
SDA
tSU :DAT
tLOW
tHD :DAT
tF
tHIGH
SCL
DATA(1)
SDA
tBUF
tPD
tDH
DATA(n)
ACK
ACK
tWR
D1
D0
(Input)
SDA
WP
Stop condition
(Output)
tSU
：
WP
tHD
：
WP
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(d) WP timing at write execution
SCL
tSU :STA
SDA
SCL
tHD :STA
tSU :STO
SDA
DATA(1)
D1
D0
ACK
tHIGH:WP
START BIT
STOP BIT
WP
DATA(n)
ACK
tWR
Figure 1-(b) Start - stop bit timing
○At
write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By
setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
Figure 1-(e) WP timing at write cancel
SCL
SDA
D0
ACK
WRITE DATA(n)
STOP
CONDITION
t
WR
START
CONDITION
Figure 1-(c) Write cycle timing
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/22
TSZ02201-0R2R0G100500-1-2
21.Dec.2017 Rev.002
BU9897GUL-W (128Kbit)
●Block
Diagram
A0 1
14bit
128Kbit EEPROM array
8bit
8
Vcc
A1 2
Adddress
decoder
14bit
Slave - word
address register
Data
register
7
WP
START
STOP
A2
3
Control circuit
ACK
6
SCL
GND
4
High voltage
generating circuit
Power source
voltage detection
5
SDA
●Pin
Configuration
(BOTTOM VIEW)
C
GND
B
SDA
A
SCL
1
WP
2
Vcc
3
GND
4
A0
GND
A2
A1
GND
●Pin
Descriptions
Land No.
C4
C3
C2
C1
B4
B3
B1
A4
A3
A2
A1
Terminal
name
GND
A1
A2
GND
GND
A0
SDA
GND
Vcc
WP
SCL
Input / output
-
Input
input
-
-
Function
Reference voltage of all input / output
Slave address
Slave address
Reference voltage of all input / output
Reference voltage of all input / output
Slave address
Slave and word address, Serial data input serial data output
Reference voltage of all input / output
Power Supply
Write protect terminal
Serial clock input
input
Input / output
-
-
input
input
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
4/22
TSZ02201-0R2R0G100500-1-2
21.Dec.2017 Rev.002
BU9897GUL-W (128Kbit)
●Typical
Performance Curves
(The following values are Typ. ones.)
Figure 2. ‘H’ input voltage V
IH
(AO, A1, A2, SCL, SDA, WP)
Figure 3. ‘L’ input voltage V
IL
(A0, A1, A2, SCL, SDA, WP)
Figure 4. ‘L’ output voltage V
OL
– I
OL
(V
CC
=1.7)
Figure 5. ‘L’ output voltage V
OL
– I
OL
(V
CC
=2.5V)
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/22
TSZ02201-0R2R0G100500-1-2
21.Dec.2017 Rev.002
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
