19-2752; Rev 0; 2/03
Quad LVDS Receiver with Hysteresis
General Description
The MAX9179 is a quad low-voltage differential
signaling (LVDS) line receiver designed for applications
requiring high data rates, low power dissipation, and
noise immunity. The receiver accepts four LVDS input
signals and translates them to 3.3V LVCMOS output lev-
els at speeds up to 400Mbps. The receiver features
built-in hysteresis, which improves noise immunity and
prevents multiple switching on slow transitioning inputs.
The device supports a wide 0.038V to 2.362V common-
mode input voltage range, allowing for ground potential
differences and common-mode noise between the driver
and the receiver. A fail-safe circuit sets the output high
when the input is open, undriven and shorted, or undriven
and terminated. Common enable inputs control the high-
impedance outputs.
The MAX9179 has a flow-through pinout for easy PC
board layout, and is pin compatible with the MAX9121
and the DS90LV048A with the additional features of
high ESD tolerance and built-in hysteresis.
The MAX9179 operates from a single 3.3V supply, and is
specified for operation from -40°C to +85°C. The device
is offered in 16-pin TSSOP and thin QFN packages.
o
Guaranteed 400Mbps Data Rate
o
50mV (typ) Hysteresis
o
Overshoot/Undershoot Protection (-1.0V or V
CC
+
1.0V) on Enables
o
IEC61000-4-2 Level 4 ESD Tolerance
o
AC Specifications Guaranteed with |V
ID
|
=
100mV
o
Single 3.3V Supply
o
Fail-Safe Circuit
o
Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
o
Low-Power CMOS Design
o
Conforms to ANSI TIA/EIA-644 LVDS Standard
o
High-Impedance Inputs when Powered Off
o
Pin Compatible with the MAX9121 and the
DS90LV048A
o
Small Thin QFN Package Available
Features
MAX9179
Applications
Laser Printers
Digital Copiers
Cell-Phone Base Stations
Telecom Switching Equipment
LCD Displays
Network Switches/Routers
Backplane Interconnect
Clock Distribution
Ordering Information
PART
MAX9179EUE
MAX9179ETE*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 Thin QFN-EP**
*Future
product—contact factory for availability.
**EP
= Exposed paddle.
Functional Diagram appears at end of data sheet.
Pin Configurations
TOP VIEW
IN1- 1
IN1+ 2
IN2+ 3
IN2- 4
IN3- 5
IN3+ 6
IN4+ 7
IN4- 8
16 EN
IN2+ 1
15 OUT1
14 OUT2
IN2- 2
11 V
CC
12 OUT2
IN1+
16
IN1-
15
EN
14
OUT1
13
MAX9179
IN3- 3
EXPOSED PAD
IN3+ 4
5
IN4+
6
IN4-
7
EN
8
OUT4
9 OUT3
10 GND
MAX9179
13 V
CC
12 GND
11 OUT3
10 OUT4
9
EN
THIN QFN
(LEADS UNDER PACKAGE)
TSSOP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Receiver with Hysteresis
MAX9179
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
EN,
EN
to GND ...........................................-1.4V to (V
CC
+ 1.4V)
OUT_ to GND .............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin Thin QFN (derate 16.9mW/°C
above +70°C).............................................................1349mW
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, C
S
= 100pF)
(IN_+, IN_-) ................................................................±16kV
IEC61000-4-2 (R
D
= 330Ω, C
S
= 150pF) (IN_+, IN_-)
Contact Discharge .......................................................±8kV
Air-Gap Discharge .....................................................±15kV
Soldering Temperature (soldering, 10s) ..........................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, differential input voltage |V
ID
| = 0.075V to 1.2V, input common-mode voltage V
CM
= |V
ID
/2| to 2.4V - |V
ID
/2|,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, |V
ID
| = 0.2V, V
CM
= 1.2V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
INPUTS (IN_+, IN_-)
Differential Input High Threshold
Differential Input Low Threshold
Hysteresis
Input Current
Power-Off Input Current
Fail-Safe Input Resistor 1
Fail-Safe Input Resistor 2
OUTPUTS (OUT_)
Open, undriven short, or
undriven parallel
termination
V
ID
= +50mV
Output Low Voltage
Output Short-Circuit Current
Output High-Impedance Current
ENABLE INPUTS (EN,
EN)
Input High Voltage
Input Low Voltage
Input Current
POWER SUPPLY
Supply Current
Disabled Supply Current
I
CC
I
CCZ
Enabled, inputs open
Disabled, inputs open
10.4
0.6
15
1.0
mA
V
IH
V
IL
-1.0V
≤
EN,
EN
≤
0V
I
IN
0V
≤
EN,
EN
≤
V
CC
V
CC
≤
EN,
EN
≤
V
CC
+ 1.0V
2.0
-1.0
-1800
-20
-10
V
CC
+
1.0
+0.8
+10
+20
+1800
µA
V
V
V
OL
I
OS
I
OZ
I
OL
= 4.0mA, V
ID
= -50mV
Enabled, V
ID
= +50mV, V
OUT
= 0 (Note 3)
Disabled, V
OUT
= 0 or V
CC
-40
-1.0
0.1
-70
0.25
-120
+1.0
V
mA
µA
V
CC
-
0.2
V
CC
-
0.1
V
TH
V
TL
V
TH
- V
TL
I
IN+,
I
IN-
I
OFF+,
I
OFF-
R
IN1
R
IN2
V
CC
= 0V
V
CC
= 3.6V or 0V, Figure 2
V
CC
= 3.6V or 0V, Figure 2
Figure 1
Figure 1
Figure 1
-20
-20
40
280
-75
25
-25
50
+20
+20
65
455
75
mV
mV
mV
µA
µA
kΩ
kΩ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH
I
OH
= -4.0mA
V
2
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, C
L
= 15pF, differential input voltage |V
ID
| = 0.1V to 1.2V, input common-mode voltage V
CM
= |V
ID
/2| to 2.4V - |V
ID
/2|,
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= 3.3V, |V
ID
| = 0.2V, V
CM
= 1.2V, T
A
= +25°C.) (Notes 4, 5, 6)
PARAMETER
Differential Propagation Delay
High to Low
Differential Propagation Delay
Low to High
Differential Pulse Skew
| t
PHLD
- t
PLHD
| (Note 7)
Differential Channel-to-Channel
Skew, Same Part
(Note 8)
Differential Part-to-Part Skew
(Note 9)
Differential Part-to-Part Skew
(Note 10)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency
SYMBOL
t
PHLD
t
PLHD
Figures 3, 4
Figures 3, 4
|V
ID
|
= 0.1V to 0.15V
t
SKD1
|V
ID
|
= 0.15V to 0.2V
|V
ID
|
= 0.2V to 1.2V
|V
ID
|
= 0.1V to 0.15V
t
SKD2
|V
ID
|
= 0.15V to 0.2V
|V
ID
|
= 0.2V to 1.2V
t
SKD3
t
SKD4
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
R
L
= 2kΩ, Figures 5, 6 (Note 11)
R
L
= 2kΩ, Figures 5, 6 (Note 11)
R
L
= 2kΩ, Figures 5, 6 (Note 11)
R
L
= 2kΩ, Figures 5, 6 (Note 11)
All channels switching, C
L
= 15pF, V
OL
(max) = 0.25V, V
OH
(min) = V
CC
- 0.2V,
44%
<
duty cycle
<
56%
200
0.77
0.74
10.6
11
4.8
4.8
250
120
80
CONDITIONS
MIN
2.0
2.0
TYP
2.6
2.52
MAX
4.6
4.6
700
400
300
900
600
400
2.0
2.6
1.4
1.4
14
14
14
14
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ps
ps
UNITS
ns
ns
MAX9179
Note 1:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Parts are production
tested at T
A
= +25°C.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, V
TL
, and V
ID
.
Note 3:
Short one output at a time.
Note 4:
AC parameters are guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 5:
C
L
includes scope probe and test jig capacitance.
Note 6:
Pulse generator differential output for all tests (unless otherwise noted): t
R
= t
F
< 1ns (0% to 100%), frequency = 100MHz,
50% duty cycle.
Note 7:
t
SKD1
is the magnitude of the difference of the differential propagation delays in a channel. t
SKD1
= | t
PHLD
- t
PLHD
|.
Note 8:
t
SKD2
is the magnitude of the difference of the t
PLHD
or t
PHLD
of one channel and the t
PLHD
or t
PHLD
of the other channel
on the same part.
Note 9:
t
SKD3
is the magnitude of the difference of any differential propagation delays between parts at the same V
CC
and within
5°C of each other.
Note 10:
t
SKD4
is the magnitude of the difference of any differential propagation delays between parts operating over the rated
supply and temperature ranges.
Note 11:
Pulse generator output for t
PHZ
, t
PLZ
, t
PZH
, and t
PZL
tests: t
R
= t
F
= 1.5ns (0.2V
CC
to 0.8V
CC
), 50% duty cycle, V
OH
=
V
CC
+ 1.0V settling to V
CC
, V
OL
= -1.0V settling to 0, frequency = 1MHz.
_______________________________________________________________________________________
3
Quad LVDS Receiver with Hysteresis
MAX9179
Test Circuits/Timing Diagrams
V
OUT
V
OH
IN_+
t
PLHD
0.9V
CC
0.5V
CC
t
PHLD
0.9V
CC
0.5V
CC
0.1V
CC
IN_-
(0V DIFFERENTIAL)
V
ID
V
CM
= ((V
IN_+
) + (V
IN_-
))/2
V
TL
V
TH
OUT_
0.1V
CC
t
TLH
t
THL
-V
ID
V
OL
V
ID
= 0
HYSTERESIS
Figure 4. Propagation Delay and Transition Time Waveforms
+V
ID
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= 0 FOR t
PZH
AND t
PHZ
MEASUREMENTS.
V
CC
S
1
Figure 1. Input Thresholds and Hysteresis
IN_+
IN_-
EN
R
L
DEVICE
UNDER
TEST
OUT_
C
L
V
CC
R
IN2
PULSE
GENERATOR
50Ω
EN
IN_+
R
IN1
V
CC
- 0.3V
OUT_
Figure 5. High-Impedance Delay Test Circuit
R
IN1
IN_-
EN WHEN EN = LOW OR OPEN
1.5V
1.5V
V
CC
+ 1.0V
V
CC
Figure 2. Fail-Safe Input Circuit
0
-1.0V
V
CC
+ 1.0V
V
CC
EN WHEN EN = HIGH
1.5V
1.5V
0
-1.0V
t
PZL
t
PLZ
50%
OUT_ WHEN V
ID
= -75mV
OUT_ WHEN V
ID
= +75mV
0.5V
t
PHZ
0.5V
50%
0
t
PZH
V
OL
V
OH
V
CC
IN_+
PULSE
GENERATOR
50Ω
IN_-
C
L
50Ω
OUT_
Figure 3. Propagation Delay and Transition Time Test Circuit
4
Figure 6. High-Impedance Delay Waveforms
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
Typical Operating Characteristics
(V
CC
= 3.3V, V
CM
= 1.2V, |V
ID
| = 0.15V, C
L
= 15pF, f = 100MHz, T
A
= +25°C, unless otherwise noted.)
MAX9179
SUPPLY CURRENT vs. FREQUENCY
MAX9179 toc01
SUPPLY CURRENT
vs. TEMPERATURE
MAX9179 toc02
DC DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
DC DIFFERENTIAL THRESHOLD VOLTAGE (mV)
30
20
10
0
-10
-20
-30
-40
3.0
3.1
3.2
3.3
V
TL
3.4
3.5
3.6
V
TH
MAX9179 toc03
110
16
14
SUPPLY CURRENT (mA)
12
10
8
6
40
90
SUPPLY CURRENT (mA)
70
50
30
ALL CHANNELS DRIVEN
10
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
INPUTS OPEN
4
-40
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9179 toc04
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
DC INPUT
(V
ID
= +150mV)
I
OH
= -4mA
MAX9179 toc05
-100
OUTPUT SHORT-CIRCUIT CURRENT (mA)
DC INPUT
(V
ID
= +150mV)
-80
3.6
OUTPUT HIGH VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.4
3.2
-60
3.0
-40
2.8
-20
SUPPLY VOLTAGE (V)
2.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
DC INPUT
(V
ID
= -150mV)
I
OL
= 4mA
MAX9179 toc06
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9179 toc07
140
3.2
3.0
2.8
t
PHLD
2.6
t
PLHD
2.4
2.2
2.0
OUTPUT LOW VOLTAGE (mV)
130
120
110
100
90
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
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