IS25LP128
IS25LP064
IS25LP032
32/64/128M-BIT
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
DATA SHEET
IS25LP032/064/128
32/64/128M-BIT
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
FEATURES
Industry Standard Serial Interface
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IS25LP128: 128M-bit/16M-byte
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IS25LP064: 64M-bit/8M-byte
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IS25LP032: 32M-bit/4M-byte
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256 bytes per Programmable Page
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Supports standard SPI, Fast, Dual, Dual
I/O, QPI, SPI DTR, Dual SPI DTR I/O,
and QPI
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Double Transfer Rate (DTR) option
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Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
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50MHz Normal and 133Mhz Fast Read
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532 MHz equivalent QPI
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DTR (Dual Transfer Rate) up to 66MHz
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Selectable dummy cycles
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Configurable drive strength
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Supports SPI Modes 0 and 3
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More than 100,000 erase/program cycles
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More than 20-year data retention
Flexible & Efficient Memory Architecture
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Chip Erase with Uniform: Sector/Block
Erase (4K/32K/64K-Byte)
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Program 1 to 256 bytes per page
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Program/Erase Suspend & Resume
Efficient Read and Program modes
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Low Instruction Overhead Operations
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Continuous Read 8/16/32/64-Byte burst
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Selectable burst length
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QPI for reduced instruction overhead
Low Power with Wide Temp.
Ranges
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Single 2.3V to 3.6V Voltage Supply
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10 mA Active Read Current
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10 µA Standby Current
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5 µA Deep Power Down
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Temp Grades:
Extended: -40°C to +105°C
V Grade: -40°C to +125°C
Auto Grade: up to +125°C
-
-
-
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Advanced Security Protection
Software and Hardware Write Protection
Power Supply lock protect
4x256-Byte dedicated security area
with user-lockable bits, (OTP) One
Time Programmable Memory
128 bit Unique ID for each device
Industry Standard Pin-out & Packages
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JM =16-pin SOIC 300mil
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JB = 8-pin SOIC 208mil
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JF = 8-pin VSOP 208mil
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JK = 8-contact WSON 6x5mm
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JL = 8-contact WSON 8x6mm
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JG= 24-ball TFBGA 6x8mm
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KGD (call factory)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
10/03/2014
2
IS25LP032/064/128
GENERAL DESCRIPTION
The IS25LP032/064/128 Serial Flash memory offers a versatile storage solution with high flexibility and
performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems
that require limited space, a low pin count, and low power consumption. The IS25LP032/064/128 is accessed
through a 4-wire SPI Interface consisting of a Serial Data Input (Sl), Serial Data Output (SO), Serial Clock
(SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) allowing more than
66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can
outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in
place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4K-byte
sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sector and block architecture
allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications
requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (Sl), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The DO pin is used to read data or to check the
status of the device on the falling edge of SCK. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve
double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Quad I/O QPI
The IS25LP032/064/128 enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode
uses four IO pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI
and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode. Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or
Hardware/Software Reset can also return the device into the standard SPI mode.
DTR
In addition to SPI and QPI features, IS25LP032/064/128 also supports SPI DTR READ. SPI DTR allows high
data throughput while running at lower clock frequencies. SPI DTR READ mode uses both rising and falling
edges of the clock to drive output, resulting in reducing the dummy cycles by half.
Programmable drive strength and Selectable burst setting.
The IS25LP032/064/128 offers programmable output drive strength and selectable burst (wrap) length features
to increase the efficiency and performance of READ operations. The driver strength and burst setting features
are controlled by setting the READ registers. A total of six different drive strengths and four different burst sizes
(8/16/32/64 Bytes) are available for selection.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
10/03/2014
3
IS25LP032/064/128
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
PIN CONFIGURATION ................................................................................................................................. 6
PIN DESCRIPTIONS .................................................................................................................................... 7
BLOCK DIAGRAM ........................................................................................................................................ 8
SPI MODES DESCRIPTION ........................................................................................................................ 9
SYSTEM CONFIGURATION ...................................................................................................................... 11
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 11
REGISTERS ............................................................................................................................................... 12
6.1 STATUS REGISTER ............................................................................................................................ 12
6.2 FUNCTION REGISTER ........................................................................................................................ 15
6.3 READ REGISTERS .............................................................................................................................. 16
7.
PROTECTION MODE................................................................................................................................. 18
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 18
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 18
8.
DEVICE OPERATION ................................................................................................................................ 19
8.1 NORMAL READ OPERATION (NORD, 03h) ....................................................................................... 21
8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................ 23
8.3 HOLD OPERATION .............................................................................................................................. 25
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 25
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ................................................................... 28
8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 30
8.7 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 33
8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 35
8.9 ERASE OPERATION ........................................................................................................................... 36
8.10 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 37
8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 38
8.12 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 40
8.13 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 41
8.14 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 42
8.15 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 43
8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 44
8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 45
8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 46
8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h) . 47
8.20 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 48
8.21 DEEP POWER DOWN (DP, B9h) ...................................................................................................... 49
8.22 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 50
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
10/03/2014
4
IS25LP032/064/128
8.23 SET READ PARAMETERS OPERATION (SRP, C0h) ...................................................................... 51
8.24 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 53
8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 55
8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 56
8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 57
8.28 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 58
8.29 NO OPERATION (NOP, 00h) ............................................................................................................. 58
8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ........................................................................................................................................................ 59
8.31 SECURITY INFORMATION ROW...................................................................................................... 60
8.32 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................. 61
8.33 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 62
8.34 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 63
8.35 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ..................................................................... 64
8.36 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) .................................................. 66
8.37 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................. 69
8.38 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 72
9.
ELECTRICAL CHARACTERISTICS........................................................................................................... 74
9.1 ABSOLUTE MAXIMUM RATINGS
(1)
................................................................................................... 74
9.2 OPERATING RANGE ........................................................................................................................... 74
9.3 DC CHARACTERISTICS ...................................................................................................................... 74
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 75
9.5 AC CHARACTERISTICS ...................................................................................................................... 76
9.6 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 78
9.7 POWER-UP AND POWER-DOWN ...................................................................................................... 80
9.8 PROGRAM/ERASE PERFORMANCE ................................................................................................. 81
9.9 RELIABILITY CHARACTERISTICS ..................................................................................................... 81
10.
PACKAGE TYPE INFORMATION ......................................................................................................... 82
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (JB) ........................ 82
10.2 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (JK) .................................. 83
10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (JL) .................................. 84
10.4 8-Pin 208mil VSOP Package (JF) .................................................................................................... 85
10.5 16-lead Plastic Small Outline package (300 mils body width) (JM).................................................. 86
10.6 24-Ball Thin Profile Fine Pitch BGA 6x8mm (JG) ............................................................................. 87
11.
ORDERING INFORMATION- Valid Part Numbers................................................................................ 88
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
10/03/2014
5
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