ISL6323
Hybrid SVI/PVI
Data Sheet
May 17, 2011
FN9278.5
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6323 dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323 supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323 features a multiphase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multiphase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a 2- to 4-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multiphase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323 features output
voltage droop. The multiphase portion also includes advanced
control loop features for optimal transient response to load
application and removal. One of these features is highly
accurate, fully differential, continuous DCR current sensing for
load line programming and channel current balance. Dual
edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients.
Features
• Processor Core Voltage Via Integrated MultiPhase
Power Conversion
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase
Power Conversion
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
(°C)
0 to +70
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6323CRZ* ISL6323 CRZ
ISL6323IRZ*
ISL6323 IRZ
48 Ld 7x7 QFN L48.7x7
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Overcurrent Protection
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
-40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2007, 2008, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6323
Pinout
ISL6323
(48 LD QFN)
TOP VIEW
VDDPWRGD
37
36
35
34
33
32
49
GND
31
30
29
28
27
26
25
13
VSEN
14
OFS
15
DVC
16
RSET
17
FB
18
COMP
19
APA
20
ISEN1+
21
ISEN1-
22
ISEN2+
23
ISEN2-
24
EN
PWM4
PWM3
PWROK
PHASE1
UGATE1
BOOT1
LGATE1
PVCC1_2
LGATE2
BOOT2
UGATE2
PHASE2
PHASE_NB
38
UGATE_NB
39
LGATE_NB
41
COMP_NB
BOOT_NB
40
PVCC_NB
42
ISEN_NB-
ISEN4+
ISEN3+
44
ISEN4-
48
FB_NB
ISEN_NB+
RGND_NB
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VCC
FS
RGND
1
2
3
4
5
6
7
8
9
10
11
12
47
46
45
43
2
ISEN3-
FN9278.5
May 17, 2011
ISL6323
Functional Pin Description
PIN NUMBER
1, 48
SYMBOL
FB_NB and
COMP_NB
ISEN_NB+,
ISEN_NB1-
DESCRIPTION
These pins are the internal error amplifier inverting input and output respectively of the
NB VR controller. FB_NB, VDIFF_NB, and COMP_NB are tied together through external
R-C networks to compensate the regulator.
These pins are used for differentially sensing the North Bridge output current. The
sensed current is used for protection and load line regulation if droop is enabled.
Connect ISEN_NB- to the node between the RC sense element surrounding the inductor.
Tie the ISEN_NB+ pin to the VNB side of the sense capacitor.
This pin is an input to the NB VR controller precision differential remote-sense amplifier
and should be connected to the sense pin of the North Bridge, VDDNBFBL.
If VID1 is LO prior to enable [SVI Mode], the pin functions as the VFIXEN selection input
from the AMD processor for determining SVI mode versus VFIX mode of operation.
If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has
an internal 30µA pull-down current applied to it at all times.
This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling
the ISL6323. If the pin is LO prior to enable, the ISL6323 is in SVI mode and the dual
purpose pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode related
functions. If the pin held HI prior to enable, the ISL6323 is in PVI mode and dual purpose
pins use their VIDx related functions to decode the correct DAC code.
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional
signal to and from the master device on AMD processor. If VID1 is HI prior to enable [PVI
Mode], this pin is used to decode the programmed DAC code for the processor. In PVI
mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down
current in SVI mode.
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the
AMD processor. If VID1 is HI prior to enable [PVI Mode], the ISL6323 is in PVI mode and
this pin is used to decode the programmed DAC code for the processor. In PVI mode, this
pin has an internal 30µA pull-down current applied to it. There is no pull-down current
in SVI mode.
These pins are active only when the ISL6323 is in PVI mode. When VID1 is HI prior to
enable, the ISL6323 decodes the programmed DAC voltage required by the AMD
processor. These pins have an internal 30µA pull-down current applied to them at all
times.
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply
and decouple using a quality 0.1µF ceramic capacitor.
A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of
both controllers. Refer to Equation 1 for proper resistor calculation
.
R
T
=
10
[
10.61
–
1.035 log
(
f s
) ]
2, 47
3
4
RGND_NB
VID0/VFIXEN
5
VID1/SEL
6
VID2/SVD
7
VID3/SVC
8, 9
VID4, VID5
10
11
VCC
FS
(EQ. 1)
With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from
FS to VCC, Droop is disabled.
12, 13
RGND, VSEN
VSEN and RGND are inputs to the core voltage regulator (VR) controller precision
differential remote-sense amplifier and should be connected to the sense pins of the
remote processor core(s), VDDFB[H,L].
The OFS pin provides a means to program a DC current for generating an offset voltage
across the resistor between FB and VSEN The offset current is generated via an external
resistor and precision internal voltage references. The polarity of the offset is selected
by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left
unconnected.
The DVC pin is a buffered version of the reference to the error amplifier. A series resistor
and capacitor between the DVC pin and FB pin smooth the voltage transition during
VID-on-the-fly operations.
14
OFS
15
DVC
3
FN9278.5
May 17, 2011
ISL6323
Functional Pin Description
(Continued)
PIN NUMBER
16
SYMBOL
RSET
DESCRIPTION
Connect this pin to the VCC pin through a resistor (RSET) to set the effective value of
the internal RISEN current sense resistors. The values of the RSET resistor should be no
less than 20kΩ and no more than 80kΩ. A 0.1µF capacitor should be placed in parallel to
the RSET resistor.
These pins are the internal error amplifier inverting input and output respectively of the
core VR controller. FB, VSEN and COMP are tied together through external R-C networks
to compensate the regulator.
Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A
100µA current flows into the APA pin and by tying a resistor from this pin to COMP the
trip level for the Adaptive Phase Alignment circuitry can be set.
These pins are used for differentially sensing the corresponding channel output currents.
The sensed currents are used for channel balancing, protection, and core load line
regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense
elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the
VCORE side of their corresponding channel’s sense capacitor.
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the
controller. Held low, this pin disables both CORE and NB controller operation. Pulled high,
the pin enables both controllers for operation.
When the EN pin is pulled high, the ISL6323 will be placed in either SVI or PVI mode.
The mode is determined by the latched value of VID1 on the rising edge of the EN signal.
A third function of this pin is to provide driver bias monitor for external drivers. A resistor
divider with the center tap connected to this pin from the drive bias supply prevents
enabling the controller before insufficient bias is provided to external driver. The resistors
should be selected such that when the POR-trip point of the external driver is reached,
the voltage at this pin meets the above mentioned threshold level.
17, 18
FB, COMP
19
APA
20, 21, 22, 23,
43, 44, 45, 46
ISEN1+, ISEN1-,
ISEN2+, ISEN2-,
ISEN3-, ISEN3+,
ISEN4-, ISEN4+
24
EN
25, 33
26, 32
PHASE2 and PHASE1 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are
the return path for the upper MOSFET drives.
UGATE2 and UGATE1 Connect these pins to the corresponding upper MOSFET gates. These pins are used to
control the upper MOSFETs and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
BOOT2 and BOOT1
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect
these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC1_2 pin provide the necessary bootstrap charge.
27, 31
28, 30
29
LGATE2 and LGATE1 These pins are used to control the lower MOSFETs. Connect these pins to the
corresponding lower MOSFETs’ gates.
PVCC1_2
The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to
any voltage from +5V to +12V depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0µF ceramic capacitor.
System wide Power-Good signal. If this pin is low, the two SVI bits are decoded to
determine the “metal VID”. When the pin is high, the SVI is actively running its protocol.
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil
driver IC if 3- or 4-phase operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core VR controller for 2-phase or
3-phase operation.
During normal operation this pin indicates whether both output voltages are within
specified overvoltage and undervoltage limits. If either output voltage exceeds these
limits or a reset event occurs (such as an overcurrent event), the pin is pulled low. This
pin is always low prior to the end of soft-start.
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return
path for the upper MOSFET drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
34
35, 36
PWROK
PWM3 and PWM4
37
VDDPWRGD
38
PHASE_NB
4
FN9278.5
May 17, 2011
ISL6323
Functional Pin Description
(Continued)
PIN NUMBER
39
SYMBOL
UGATE_NB
DESCRIPTION
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-
controlled gate drive for the upper MOSFET and is monitored for shoot-through
prevention purposes.
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect
this pin to appropriately chosen external bootstrap capacitor. The internal bootstrap
diode connected to the PVCC_NB pin provides the necessary bootstrap charge.
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-
controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the lower MOSFET has turned off.
The power supply pin for the internal MOSFET driver for the Northbridge controller.
Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET
gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor.
GND is the bias and reference ground for the IC. The GND connection for the ISL6323 is
through the thermal pad on the bottom of the package.
40
BOOT_NB
41
LGATE_NB
42
PVCC_NB
49
GND
Integrated Driver Block Diagram
PVCC
BOOT
UGATE
PWM
20kΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
10kΩ
PHASE
LGATE
5
FN9278.5
May 17, 2011
瑞萨MCU/MPU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
